Impact errors programing V4LX25

Howdy Rudi,

Sorry I can't be of any help, except to say that, as the JTAG faq shows, you've got to keep trying.

Make sure the JTAG clock looks good at the via under the LX25. Bypass the data around other devices (if you have it going through them). Hold you nose just right. Wait for a full moon. I wish I were kidding.

Marc

ROTFL

hold yor nose! Yes that seems to be the only thing todo if iMpact and xilinx cables have download problems. We just had a Platfrom Flash that had increasing failure rate on programming using xilinx Cable III until it did not program at all, giving erase errors. Changin to Cable IV did fix the Erase error. Beats me. Well I also have seen boards that can not be programmed at all with Cable IV but program without any problems using 5 wires to LPT port.

I think mr Usselman is using a LX25 Board from Memec so he cant change much on the board, it is supposed to work!

So yes, the nose trick is the only one left! I wish i would know how to hold my nose properly, too much rain is coming in :(

antti

Yes I am using the Memec Insight Virtex 4 LX25 boards, Just got three of them today. I kind of assumed that the boards coming from Memec-Insight are professionally designed and reliable. Thats why we for out the big bucks for these boards. Of course I placed an inquiry with them as well, just wanted to see who is faster, the net or Memec ... will post an update as soon as I have a solution ...

Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Another bit of information:

I did try to reduce the speed of the programming cable to

200 KHz - didn't make any difference.

It appears as my target application does work correctly even though of the reported errors. Perhaps bitgen/impact are not quite Virtex 4 tested/debugged ?

Anybody here ever programed a Virtex 4 LX 25 ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

The 4VLX25 has an issue with the timing of the last bit shifted out on TDO in that TDO tristates too early. This results in the final bit being misread, typically as a 1. Sadly, the last bit in the device status register is the CRC bit and this results in the the warning message you see. This issue is detailed in the device errata

al> Hi !

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Thanks Niel, got the doc.

Does this explain the 52 mismatches I get during compare as well ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Niel,

unfortunately the work around does not work on Linux. Bit Gen Core dumps (Segmentation fault) when specifying the option for serial configuration.

Are there any other solutions ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Neil,

I would like to develop a real solution for the above problem. I am stuck with 3 Memec-Insight boards, which Memec refuses to replace for boards with Production Parts. Right now those boards are pretty much useless (no programming, no chipscope), as they provide directly a connector to a parallel cable 4. I need to build a gizmo, that will allow me to fix/work around this problem.

There is also a (xilinx) CPLD that can be included in to the scan chain, but by default it would be before the FPGA.

Now, If I can mode the CPLD after the FPGA in the chain, and add a delay to CPLDs TCLK input, would that solve the problem ?

How big of a delay would I have to add ? Can you, or some other Xilinx soul give us a bit more technical data about the late TDO, so we can engineer a reliable solution ?

Or any other practical solutions would be highly appreciated.

Thank you !

Kind Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Rudi,

I know we have a simple workaround that we use in the fpga lab.

But, I am not in San Jose right now, so let me look into when I return on Friday.

Aust> Neil Glenn Jacobs>

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Rudolph,

Making the CPLD the last device in the chain should make the issue go away since the CPLD seems to be able to sample the TDO before is tristates.

It is also known that the new Platform Cable USB makes this problem go away because it samples the TDO earlier.

I believe that Aut> Neil Glenn Jacobs>

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Hi Rudi for iMpact: install 3 jumpers in JP14 fixes CRC error during Download. for ChipScope wait for ChipScope bugfix !!! ChipScope just doesnt work :(

Antti

hi I maybe have to take my prev message, partially - i used EDK+Chipscope design for testing so USER1 was used by MDM, and as of V4LX25 errata USER2 is not available, so Chipscope might still be useable in designs where MDM is not utilized eg USER1 is free.

But I have not yet verified this.

confirmed: chipscope can be used, in case the PLD is added to chain (the 3 jumpers fix in V4LC board) when bitstream is loaded with impact and chipscope ICON sits on BSCAN/USER1. downloading with chipscope does not work, simultanuous use of MDM and Chiscope in EDK doesnt work.

antti

I did try that and my in my environment chipscope did NOT work. It only recognized some of the ILA configuration but could not capture any data.

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

I did try that and it did not work with any of the 3 boards I have.

Unfortunately that does not work with linux so it's not an option for me at this point.

Yes I did receive several emails from Peter, and will try those solutions tomorrow.

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

BTW, the PLD is add in front of the FPGA, so it does NOT fix the TDO timing (which goes directly to the cable).

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Thanks to the excellent support from Xilinx this problem has been solved !!! Turns out the Memec-Insight board had a 100 ohm (yes 100 !) pull-up on the TDO line. That basically broke everything.

Removing the pullup, got rin of the CRC bit errors and chip- scope appears to work now as well.

Thanks a lot for going the extra mile, to all the good folks at Xilinx !

Kind Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

"Rudolf Usselmann" schrieb im Newsbeitrag news:cu9leb$rv5$ snipped-for-privacy@nobel.pacific.net.sg...

can you download with ChipScope as well after removing the pull-up ? we can use ChipScope but can not download with it, well I have not yet removed that pullup resistor

Antti