Hello,
i'd like to have some informations about image compression on FPGA hardware. Do you have some experiences with the Matrox Solios and in special the version with the Altera FPGA? I need some informations how much time it could take to implement compression algorithms on FPGA and how to get an idea how many gates are needed. Are there other solution than the one from Matrox?
Thanks a lot,Eric
Hi Eric,
we have JPEG compression/decompression-IP-cores (no info yet on our web-page, sorry...), which are fast and small (but not free). Of course they are also usable for MJPEG (which are just JPEG-pics one after another).
To give you an idea about the size: JPEG-Encoder (YUV4:2:0), Cyclone II:
2350 LEs 4 M4K-blocks 14 9bit-multiplier-elements (=7 18x18-multipliers)But it is really optimized for size, so I think it will be difficult to achieve this size with another solution.
Performance: >120MHz in slowest speedgrade (->80MPixel/s peak compression rate)
Regards,
Thomas
Elphel has an open-source FPGA-based camera system. I believe it does compression. You can grab their source from their website
-- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)
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