Hi,
I am very interested in exploring the use of ICAP for self-reconfiguration of the Virtex2 fpga. XAPP 662 describes the in-system reconfiguration of RocketIO attributes, and I have been trying to understand the process of self-reconfiguration through this application note as well as the reference design that comes with it.
It seems that we need to configure the FPGA with a bitstream generated from hdl that includes an PLB bus arbitrator and controller, as well as ICAP IPIF to the PLB. Does this mean the ICAP, possessing access the configuration memory, would actually have access to parts of the configuration memory that defines the arbitrator and ICAP IPIF as well? Or are is the information used to configure the arbitrator and IPIF somewhere else? Say for instance the fpga is to be configured with a jpeg encoder. Would the configuration memory accessed by the ICAP be solely occupied by the jpeg encoder configuration, or by the ipif etc as well? If in the latter case, then ICAP should never modify areas defining the IPIF, is this correct?
I would appreciate too if someone who has done this before can provide some guidelines on how I can set the system up to use the ICAP. Thanks in advance!:)
Ju Hwa