IBUFG incapable of driving both CLKDLL and BUFG simultaneously?

I want my master input clock, which is on a dedicated pin, to clock most of my logic through a BUFG. I also want it to drive a CLKDLL so I can use the CLK90 output.

After much head-banging I assert the following: On a Spartan IIE, an IBUFG output cannot be routed to both a CLKDLL input AND a BUFG input simultaneously.

Synplicity will synthesize this setup beautifully, but the Xilinx Placer won't accept it.

Yes, I know I could use the CLK0 output through a BUFG instead of my original clock, but my input clock can change speeds abruptly, which will cause the CLKDLL to unlock and exhibit undefined behavior until relocked. This makes me nervous and I'd rather just use my original input, thank you.

A double mocha to he or she who can disprove my assertion.

-td

Reply to
Tony Dean
Loading thread data ...

Tony,

You should be able to do this:

Connect the IBUFG to a BUFG. Connect the DLL input to the output of that BUFG. Use another BUFG on the DLL's 90deg output.

Bob

Reply to
Bob

Hi Bob, I agree, you should be able to do this. But you can't, or at least I can't. I'm getting a Place error on something as trivial as:

input_clk_buf : BUFGP port map (I=>extclk, O=>dll_in_clk); dll_fb_buf : BUFG port map (I=>dllout_clk0, O=>dll_fb_clk); dll90_buf : BUFG port map (I => dllout_clk90, O=> clk90); dll : CLKDLL port map(CLKIN=>dll_in_clk, CLKFB=>dll_fb_clk, CLK0=>dllout_clk0, CLK90=>dllout_clk90, etc.);

The BUFGP is just a IBUFG+BUFG, like you suggest. I still get the following Place errors:

ERROR:Place:106 - Could not find an automatic placement for the following components: dll90_buf of type GCLK BUFFER is unplaced. input_clk_buf/BUFG of type GCLK BUFFER is unplaced. extclk of type GCLK IOB is unplaced. dll_fb_buf of type GCLK BUFFER is unplaced. dll of type DLL is unplaced. ERROR:Place:107 - Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components.

Is it just me?

-td

Reply to
Tony Dean

This seems strange because I just tried this on a Spartan II (not E) with Foundation Schematics and it does let me connect the IBUFG to both a DLL and a BUFG. I verified this in the FPGA Editor.

Unfortunately the Foundation tools don't support the Spartan IIE so I tried the same thing with ISE 6.1i and found that it won't allow the dual connection for the Spartan II as well as the IIE. That tells me that the tools are doing this to you, not the part. I suggest opening a web case with Xilinx

Reply to
Gabor Szakacs

Reply to
Marc Guardiani

You may have to put LOC constraints on the BUFGs and CLKDLLs. The automatic placer doesn't do so hot a job figuring out which BUFGs should be next to which CLKDLLs. The usual result is that error message.

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
formatting link

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Reply to
Ray Andraka

There is a bug in ISE 6.x. You should manually LOC the IBUFG, BUFGs, and DLL. LOC the BUFGP on the same side as input clock and LOC DLL, FB BUFG and CLK90 BUFG on the opposite side. Good luck.

Reply to
GSM User

placer doesn't do so hot a job figuring out which BUFGs should be next to which CLKDLLs. The usual result is that error message.

Problem solved! While Marc Guardiani deserves Honorable Mention for his workaround, "GSM User" and Ray Andraka have the correct answer and are entitled to the double mocha. I had discovered the same fix shortly before and am pleased to have my findings confirmed. The clue was in the hitherto-ignored error message: ERROR:Place:107 - Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components. What this actually means apparently, is that Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components. Details for this can be found in the bowels of the Xilinx documentation at:

formatting link

I'll forward this little tip on to the Xilinx FAE whom I opened a WebCase with, who apparently is not aware of this detail.

Mochas are payable in person at any cafe here in Santa Cruz. In the event that transportation costs to and from Santa Cruz exceed the cost of a double mocha ($3), please supply PayPal address to which said amount can be promptly remitted.

Thanks to all,

-td

Reply to
Tony Dean

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.