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I2S serial to parallel conversion and generating C,V and Z bits

Hi, I'm working on interfacing I2S audio and am new at doing this. Could someone describe how I2S serial data (20-bit left justified format) is converted to parallel format and the Channel status, Valid and Z bits are generated. Any links to VHDL/Verilog code would also be of great help.

Thanks, cbr

Reply to
cbr_929rr
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cbr_929rr schrieb:

google: i2s verilog

after 12 seconds you are there:

formatting link

is it really so hard to find that you have to ask?

Antti

Reply to
Antti

Thanks for the quick reply. The link seems to be working now but I've had trouble accessing opencores even a few minutes ago.

I am not able to find info on how to generate the control bits in the description or the code. It would be very helpful if someone could describe this.

Thanks, Cbr

Antti wrote:

Reply to
cbr_929rr

The very first result of a Google search for "I2S channel status" was:

formatting link

-a

Reply to
Andy Peters

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