I/O short circuit protection?

On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect the outputs from possible miswiring to GND or +3.3V or Output-2- Output. Is there any common practice way to accomplish this?

I'm considering a 2.2k series resistor array "chip". But maybe there's a more appropiate way? Also what's the reaction of loading the output with say a 300 ohm resistor and specifying 16 mA drive?

Reply to
posedge52
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The other chips is an 10/100Mbps ethernet PHY (25 MHz/40ns). And the concern is shorts to either GND or +3,3V (no 24V).

Reply to
posedge52

Are you designing a board with a production run of three that you'll be assembling with the toaster-oven technique?

If you're using a professional assembly house, there is post-assembly testing that will test for shorts. If you have a production run too small for a bed-of-nails tester, there are still flying-lead manufacturing defect analyzers that can check your board for shorts.

Why design in "protection" that limits your signal characteristics when all you're protecting from is manufacturing faults? If you were cycling connecting the FPGA in and out of a connector over and over to varying equipment, I could understand some concern. But for soldered-on chips?

There are better ways.

Reply to
John_H

Putting 2.2k series resistors in signals that will be expected to have rise and fall times of one or two nanoseconds is very unlikely to work. Think about it. The time constant of a 2.2k resistor in series with a 5pF input capacitance is 11ns - an order of magnitude higher than your edge rate and almost comparable to the actual cycle time.

As others have said, don't waste time designing for possible manufacturing defects and compromising your design in the process. I would argue that the only time you would do this is if a defect could cause major problems such as fire or risk to life, neither of which is likely on a low-voltage, low-power board.

Reply to
David Spencer

It's for a test setup, where I will test different fpga device setups. No production run at all, not even a prototype one. I have bought a 100 ohm series resistor net package. Which will limit any shorts to 33mA. And I think the rise times will be ok with this. t = RC = 100*10pF (worst case Sp3E) = 1ns. The sp3e datasheet says max

100mA, I hope this will protect the fpga for those minutes it takes to test the setup.
Reply to
posedge52

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