I look for a wideband SERDES chip

Hello I have got a problem in SERDES chip selection that I would be grateful if someone helps me in this regard. First, I explain the system that we have. We want to design an STM-4 SDH system which has 5 tributary cards and 1 optical STM-4 line card.The tributary cards are of two types : E1 card and data card. The E1 tributary card which contains an SDH E1 mapper, has a 12-pin telecombus in 19.44 MHz rate in each of its transmit and receive directions (each card has 24 pins in backplane). but the Data tributary card which contains an EoS device on itself, has a 12-pin telecombus in 77.76MHz rate in each of the transmit and receive directions.The pslot of the optical line card is fixed but each of the tributary cards can sit in any position of the 5 tributary slots. to reduce the number of the pins on the backplane we want to serialize the telecombuses between the optical line card and the tributary cards. Since we do not know which of the tributary cards is inserted in in each slot we should select a SERDES which can serialize the data from both of the rates of 19.44 and 77.76 MHz (But during my searches in different vendors I haven't been able to find such a chip). I have got 2 questions.

1- As I have seen in different vendors pages, most of the SERDES devices are placed after a protocol device. for transmitting SDH
Reply to
Arash
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Since STM4 is only 622 Mb/s and you're posting on the FPGA board, you can apply a SerDes from just about any FPGA to get to your rate Many families will also support 622 Mb/s in the standard I/Os. The STM-4 rate is a target for most FPGA vendors so they'll shoot at this as an achievable maximum on standard I/O and a minimum on the SerDes as well.

The SerDes are often used after the protocol layer but isn't needed in an application with protocol. The FPGAs have this functionality as a more generic function than you might perceive.

Two cautions for your application:

First, the clocks must be supplies separately for your links; the FPGA logic doesn't deal well with plesiochronous signals alone though some SerDes blocks might support some form of clock recovery. If you have the local clock available and can communicate that clock with the 622 Mb/s data, you should be in good shape.

Second, these signals can *not* be used for timing. The jitter requirements for the SDH signals are sincerely more strict that what you should expect from the FPGAs. As with most SDH designs, you should only introduce signals onto the line that are within the ITU-T jitter limits.

As long as all your data shuffling is internal to your system and you're retimed for all your transmitters with the appropriate low-jitter circuitry, today's FPGAs can really carry you well.

Oh - and did you have two questions?

- John_H

Reply to
John_H

Hello and thanks for your cooperation. Sorry, since I copied this script from another place, during the copy, the last question was not pasted correctly. Anyhow, my two questions were as follows:

1- As I have seen in different vendors pages, most of the SERDES devices are placed after a protocol device. For transmitting SDH telecombus data is it necessary to implement a protocol on it or not. (Why protocol specification is required?). 2- Has any> Since STM4 is only 622 Mb/s and you're posting on the FPGA board, you can

First of all, SERDES is not available in any FPGA, and for example in Xilinx FPGA's, it is available in VIRTEX-II pro and the VIRTEX-4 and VIRTEX-5 familes. do you know any low price small FPGA which supports the SERDES feature as we want. (In our current design the telecombuses from the tributary cards are directly connected from the tributary cards to the FPGA on the OIU card). Meanwhile, if we don't want to have SERDES, and just use the ordinary I/O's for communication, we would need a (233.28MHz=19.44Mhz*12) 233.28 MHz clock in each of the E1 tributary cards and a 933.12 MHz clock on the data card to transmit the 12-bit telecombuses serially. Meanwhile we should also transmit the 233.28 MHz and 933.12MHz clock on the backplane. Am I right? have you any other idea about this?

They won't surely be used for timing.

But we should be sure that neither of theses 12 bits are shuffled. Because the SDH chip needs these 12 signals in its correct timing position.

Reply to
Arash

A Serializer/Deserializer (SerDes) can be implemented as a hard silicon block with (relatively) clean PLL-based VCO or it can be implemented in general FPGA log, taking parallel data in to produce serial data (Ser) or taking in serial data and making it parallel (Des). By using the inexpensive FPGAs capable of high LVDS I/O rates, you can get most of what you need pretty readily without resorting to the hard SerDes block which - while capable at the slow 622 Mb/s rate (in the SerDes realm it's slow) they are more geared toward STM-16 style rates.

You confuse me with the 933.12 MHz clock need since you're dealing with STM-4 rates as the basis. If you have full STM data plus 50% overhead then I'd suggest having two channels plus clock rather than one channel plus clock would be prudent.

You are correct in that this scheme - fabric-based SerDes functionality

- would require a separate clock for each independent timing source. Some hard SerDes blocks in the more expensive (higher functionality) FPGAs can do clock recovery but many of those require 8b/10b encoding which is *fine* if you're dealing with FPGA based distribution where you have complete control over both ends.

I still can't stress enough how any timing that passes through the FPGAs can be used for timing the data to the internal logic but *cannot* be used as a raw, clean timebase for the STM transmitters.

You might find a Xilinx App Note of interest, though the implementation is not well suited to the inexperienced FPGA designer. Dealing with high speed chip-to-chip data transfer, the following App Note can deliver many parallel channels of STM-4 class speed.

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You might even f> Hello and thanks for your cooperation.

Reply to
John_H

In every parallel SDH telecombus, there are at least 4 other signals apart from the 8 data bits which accompany the data signals to show the different specific byte places in the frame. (Like the J1 pulse). For example in an STM-4 system, there is a 77.76 MHz data bus accompanied with one parity , one pin Clock,one C1J1V1 pin and one SPE pin and hence the telecombus would be a 12 pin bus.

Reply to
Arash

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Probably an overkill for your requirements but if the price is right why not?

If you insist on solution based on low-cost FPGA I'd recommend a compromise - parallel DDR bus with 3 data lanes running at 311MT/s. Internally FPGA would run at 155.52MHz which is manageable even for cheap Cyclon2 or Spartan3.

Reply to
already5chosen

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