this is my code:
entity Top_Module is port ( o_DSP0 : out MyRecordType ); end Top_Module;
whe o_DSP0 is:
type MyRecordType is record int4 : std_logic; int5 : std_logic; int6 : std_logic; int7 : std_logic; end record;
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How is o_DSP0 declared in ucf file?
A vhdl port type is declared in a package file. The package file must be listed in the synthesis file list, above all files using the package.
-- Mike Treseler
RecordType
Most likely the 'o_DSP0' signal will get synthesized to a 'flattened' set of names like 'o_DSP0_int4', 'o_DSP0_int5', etc. Check the output of your synthesis result to find out how the record type signal elements got renamed.
KJ
I tried this recently and had that result: I had wanted the signal names "int4", "int5", etc., but got the "flattened" names. -Kevin
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