Hello,
I can not simulate "pipelined divider v3.0" .My verilog code is below:
`timescale 1ns / 1ps
module divide(dividend,divisor,quot,remd,clk,rfd,ce);
input [7 : 0] dividend; input [7 : 0] divisor; output [7 : 0] quot; output [7 : 0] remd; input clk; output rfd; input ce;
d1 div1(dividend,divisor,quot,remd,clk,rfd,ce);
endmodule
when i synthesize this code xst gives no error but i cant simulate this code. when i try to simulate it, i take 2 errors
ERROR:HDLParsers:3482 - Could not resolve instantiated unit SDIVIDER_V3_0 in Verilog module work/d1 in any library ERROR:Simulator:198 - Failed when handling dependencies for module test3
May someone help me about it please. How can I work it?