Since the max serial-slave configuration rate on things like Spartan3 chips is, what, 20 MHz or something, you might consider slowing down the CCLK input path, and/or adding some serious hysteresis on future parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads and stubs and vias and such, so may not be as pristine as a system clock. CCLK seems to be every bit as touchy as main clock pins, and it really needn't be.
John
John,
Are your suggestions for the CCLK generated by the Xilinx device or the CCLK received by the Xilinx device?
I think the max speed is up to 66 MHz these days in the Spartan3E. It may not be LVDS rates but it's not 4000 series logic, either.
- John_H
What it's really saying is that when designing a PCB, CCLK should be treated with as much care and respect as any other clock signal so you won't have lots of loads, stubs and vias and such.
KJ
And what I'm saying is that treating it as such shouldn't be necessary.
John
In serial-slave mode, the FPGA receives CCLK.
Right. Improving the noise immunity of the CCLK receiver would have exactly one practical result: more FPGAs would configure.
John
Wouldn't one expect this to be 'normal design practise' ?
I suppose Xilinx missed that obvious feature, becasue there are no other Schmitt cells on the die, and even tho the CPLDs have this, I'm sure their inter-department sharing is like most large companies :)
-jg
Hi John,
Thank you for the feedback. Fortunately, this is already a planned enhancement on future families.
--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs
--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
Thank you! Thank you!
Maybe I'm not crazy after all. Maybe.
Next, how about making the real clock inputs programmable to be slower and less noise sensitive? Yeah, some people are never satisfied.
John
I have it secondhand (one of my guys tells me) that all S3 inputs have about 100 mV of hysteresis. But that's not enough to improve noise immunity in most practical situations.
It's good that FPGAs keep getting faster, but not all applications need all that speed, and pickiness about clock edge quality can be a real liability in a lot of slower applications.
John
True - there is also a slight speed penalty for the full schmitt cells, so that's a reason why the speed-at-all-costs FPGA sector ignores the benefits. Still, the news from Steve K is good :)
-jg
Right. As noted in another thread, one can always add a deglitch circuit to any input, including clock pins, except for CCLK. So if that's the only one they slow down, we may elect to routinely deglitch system clock inputs except when we really need the speed.
I suppose they'll schmitt the jtag pins, too; I don't use them, but they seem like great candidates for noise problems.
Purists will argue that once the sacred word "clock" is voiced, we are obliged to drive it appropriately. But it's getting so that a 5 ns rise with a couple hundred mV of noise is not a reliable clock any more, and designing brutally fast, star-distributed clocks into a slow industrial-environment product really doesn't make a lot of sense.
I'd hazard that the majority of FPGAs are used at a fraction of their speed capability.
John
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