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HSTL classes and termination schemes

JEDEC defines various classes and termination schemes for HSTL: I unterminated or symmetrically single parallel II source series or symmetrically double parallel III asymmetrically single parallel IV asymmetrically double parallel

What I'm missing is an answer to my question: Where to use which termination scheme? In my special case: Connecting one QDR SRAM to a FPGA by HSTL interface, providing different types of signals: differential (clocks), single-ended unidirectional (address, control) and single-ended bidirectional (data).

Who can assist?

Roland.

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Roland
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I designed with QDR a while ago. I'm sure that the datasheet is quite specific about the requirements of every pin. In particular the whole point of QDR as opposed to DDR SRAM is that there are no b-directional signals. Also there are no differential clocks. There are, however, clocks that need to be sent in anti-phase with each other but this is for timing/functional reasons not for signal quality reasons.

Colin

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colin

I've just jogged my memory some more. For QDR1 memories and 100 and something MHz it made no difference to functional test or looking with a quality scope whether the series resistors in the FPGA was used or not.

Col> Roland wrote:

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colin

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