Does anybody out there have a working design using a virtex 2 with an "FG" package type and HSTL signals? Currently I have a design with an HSTL clock coming from the fpga to a self-terminating Samsung QDR memory. I am having major problems getting it to work. As I increase the frequency the amplitude of the signal decreases. At 25 MHz I get a 1.4 V signal, and at 100 MHz I get a 200 mV signal. The memory does not even work until a clock speed of 130 MHz can be reached.
I am aware of designs using a virtex 2 with an "FF" package type. I don't want to go into detail but I have performed several tests and am suspecting there is something wrong with the virtex 2 "FG" package type and HSTL signals. If anybody out there can tell me they have something working it would tell me that I am wrong and it is something else. Please only reply if you have an actual working board or if you have also failed to make a "FG" virtex 2 part work.
Here is some information on the traces,
It is a point to point connection less than 3/4 of an inch the line impedence was measured with TDR and it is between 50 and 53 ohms