I have some problems with a design I am porting from Xilinx to Altera. The fitter dies with a message about the design not fitting into the device.Further investiogation shows that Quartus tries to move a lot of small shiftregisters (32-bit x 4) into M4Ks, which is a not the best use of my embedded memories...
Can anyone explain to me why this happens? I am using 75% of the FPGA right now and should be able to get the small shift registers into LEs. Is there any way to let Quartus infer none or _some_ of the shift registers into M4Ks and use LEs for the rest??
(I am using Quartus Webpack version 8.0, build 231 07/10/2008)
thanks for any help