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how to use register to save data

There are Matrix 4 by 4 R and Vector 4 by 1 B generated in Matlab. I transmitted these data to FPGA board. The 16 elements of R are saved in a RAM and the 4 elements of B are saved in another RAM. Now I am thinking if it is possible to save these data in several registers.

For example: for k=1:4 B= B*2^mdiff - R(:,k) end

midff is a constant. It is seen that B do update once need read R RAM and B RAM 4 times. So i wanna to save these data in several registers. Then B can do one update operation in one clock cycle by reading all the data at the same time. But if i put one register following every element, i don't know how to index these different registers. Does anybody tell me how to figuer it out? Many thanks.

Reply to
ZHI
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Can I try this way?

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0); signal arrayb: array_type1 :=(others=>(others=>'0'));

I define the array_tpye and store the elements into the arrayb. I don't know if it is proper solution.

Reply to
ZHI

Can I try this way?

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0); signal arrayb: array_type1 :=(others=>(others=>'0'));

I define the array_tpye and store the elements into the arrayb. I don't know if it is a proper solution.

Reply to
ZHI

Can I try this way?

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0); signal arrayb: array_type1 :=(others=>(others=>'0'));

I define the array_tpye and store the elements into the arrayb. I don't know if it is a proper solution.

Reply to
ZHI

ZHI schrieb:

Hi Zhi, how do you "transmit" the data to the FPGA Board? are you using some tool like system designer that buids your bridge from matlab to the FPGA?

Your problem would be simple to solve, if you were designing your datapath yourself in VHDL or verilog. But with automated translation tools you have to figure out how to write matlab code in a way that will be interpreted in the way you intend, rather than the standard solution you get now.

Matlab sees every variable as a matrix. The most natural way of storing matrices is ram. So the disigners of your translation tool choose this solution for simplicity and generality. If you want something special e.g. to speed up your design you have to tell the tool.

My guess would be (and it's really just a guess!) that you have to specify a scalar variable for each matrix element, and don't use loops cause loops may infer a copy from ram to register machine which would not be what you intend.

have a nice synthesis Eilert

Reply to
backhus

I transmitted these data to FPGA board by a serial link from Matlab. I use the serial commond like fwrite(s,R,'int8','async') to send the data to UART. I did not use the translation tools. Now I am thinking can I try this way:

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0); signal arrayb: array_type1 :=(others=>(others=>'0'));

I define a new type and store these elements in the array type instead of the RAM.

backhus wrote:

Reply to
ZHI

Hi Zhi, OK, so you are just feeding the matlab data to the FPGA and write your algorithm in VHDL yourself.

If you are defining an array type as described above it depends on the rest of your code whether your synthesis tool creates a ram or not.

if yo access all elements of the array at the same time, the synthesis tool will be forced to produce some parallel hardware using registers

e.g.

for i in arrayb'range loop arrayb(i)

Reply to
backhus

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