Hi all: I have the following verilog codes which shift the serial data to parallel data.But it cost too much LEs in Altera FPGA.Then I want to make it wokes in EAB.I do not what to do.Anybody would help me?
reg[31:0] reg_in[7:0],reg_out[7:0];
always @(posedge clk) begin if(reset) cnt8