how to use both FFs in a CLB's slice using LOC or RLOC

"AugustoEinsfeldt":

Maybe this isn't a really answering any of your qestions, but maybe you'll be interested in xdl.

If you're using windows, there'll be an html-file describing xdl in /xilinx/help/ instead of /xilinx/doc/

Gruss

Jan Bruns

Jan, thanks for this hint. XDL is a powerfull way to get the details I want, indeed. I will study it and shall build some simple tool to automate part of the work. Anyway, I will keep the hope to accomplish something in my first post using statements included in VHDL source files. It would make easier maintenance and debugging.

-Augusto

To constrain two FFs to a slice, all you need to do is assign them both the same RLOC or LOC constraint.

Bret

You can just use the same RLOC attribute for both FFs or XORCY primitives.

If you want to specify a specific LUT, FF, XORCY within the slice, you need to also use the BEL attribute. Read about it here:

Attributes can be specified either in the UCF file or in the VHDL/Verilog source. Look in this document:

on page 222

There are direct routing constraint, but they are very hard to use, and require manual routing in the FPGA editor.

For most applications, it would be better to use exhaustive timing constraints to specify your design requirements, and let the tools select the resources to acieve the requirements.

While I don't agree with the sentiment, Xilinx's attitude is that if the constraints are met, the choice of resources should be irrelevant to the user.

Other tools that may interest you other than the FPGA editor, are JBITs tools (no support for most recent products), and XDL (limited documentation, but complete access to the underlying design database. An enthusiastic engineer can derive sufficient understanding by examining XDL files, and do experiments in the FPGA editor, and seeing the resulting XDL. Same thing for directed routing).

I don't believe such documentation exists. After you have used these products for about 16 years, it will start to come to you.

Philip

Philip Freidin Fliptronics

Thank you, Philip and Bret for the replys. I am working with Xilinx FPGAs for 9 years but never went the deep and speed I'm doing now. MAP was resulting an error when trying to assign two FFs in a same slice. Found why: I am using different clock sources for FFs and it is only one per slice. Still, I have to solve a signal net distribution that PAR seems to having a hard time to meet the constraints. After using a TBUF to feed the signal in a longline the timming improved but not enough. I could (and will soon) move from current SP2E to a SP3 and let the tools to do the job but it is a good opportunity to learn more about using resources and building something very close to the device's architecture. My first attempt this way was around 5 years ago writing a tool to automate a dinamic reconfiguration process (before JBITs) in a XCV50 device. Pure research lost the fight against design jobs (the money, in the end) and I left the deeper FPGA for another moment. XDL is very promissing and shall work a bit on it. Thank you for your supporting.

-Augusto AEE Engenharia Eletronica - Brazil

RxCy.FFX or RxCy.FFY, I think...

oops, wrong syntax: the above no longer works, has been replaced by INST "I3/Q_14" RLOC = "X0Y7" | BEL = "FFX" ;

(in UCF format; there is something similar in VHDL, refer to constraint guide for details but I think you have to attach separate RLOC and BEL attributes to each instance in VHDL)

I think it's RxCy.XORF and RxCy.XORG, to go with the F and G LUTs in the slice. Modified as above...

That's where I think you need XDL.

Once you know what to look for you can search for it, (most of the above is in the "constraints guide") but there's not much in the way of worked examples.

Be aware that 6.3 tools have issues handling these constraints, which Bret Wade assures me are resolved in 7.1 (which I haven't downloaded yet, I'm on a modem...)

is (a) a worked example using UCF attributes (and "black_box" attributes in VHDL), and (b) an illustration of some of the 6.3 issues... it successfully places 2 out of 8 instances, the others have a variety of bizarre mis-placements.

Essentially, if an RPM has *something* in its lower left hand corner; AND if all RPMs are placed on even X and Y locations, everything works smoothly. Otherwise...

- Brian

RxCy.FFX or RxCy.FFY, I think...

oops, wrong syntax: the above no longer works, has been replaced by INST "I3/Q_14" RLOC = "X0Y7" | BEL = "FFX" ;

(in UCF format; there is something similar in VHDL, refer to constraint guide for details but I think you have to attach separate RLOC and BEL attributes to each instance in VHDL)

I think it's RxCy.XORF and RxCy.XORG, to go with the F and G LUTs in the slice. Modified as above...

That's where I think you need XDL.

Once you know what to look for you can search for it, (most of the above is in the "constraints guide") but there's not much in the way of worked examples.

Be aware that 6.3 tools have issues handling these constraints, which Bret Wade assures me are resolved in 7.1 (which I haven't downloaded yet, I'm on a modem...)

is (a) a worked example using UCF attributes (and "black_box" attributes in VHDL), and (b) an illustration of some of the 6.3 issues... it successfully places 2 out of 8 instances, the others have a variety of bizarre mis-placements.

Essentially, if an RPM has *something* in its lower left hand corner; AND if all RPMs are placed on even X and Y locations, everything works smoothly. Otherwise...

- Brian

Thanks, Brian. I'm just moving to 7.1 to skip some problems I found when translating NCD to XDL, and also in the hope to have improved PAR. I will use BEL attribute to improve results in the signal distribution before going deeper in XDL. As I said before, I'm facing a very good opportunity to learn fine placement and your directions are a great help. Thank you.

-Augusto