How to transfer multiple bit data between phase shifted clock?

Different phases of the same clock are not asynchronous. There is a defined timing relationship between clk and clk_90 in your case, right? If the dat a can propagate between the two phases within that time (less setup), then you can just transfer the date directly between registers clocked by each p hase with no problems.

If the time is not long enough, there are other choices:

You have four clock edges total. You can use more than just the initial and destination edges in your transition, and you don't have to do it all at o nce. Assuming clk_90's rising edge is a quarter period after clk's rising_e dge:

You could transfer from rising_edge(clk) to falling_edge(clk_90) in 3/4 per iod), and then to rising_edge(clk_90) in 1/2 period.

Or you could transfer from rising_edge(clk) to falling_edge(clk) in 1/2 per iod, and then to rising_edge(clk_90) in 3/4 period. Either of these allows at least a half clock period to propagate the data in each step.

If you cannot make the transition in half a clock period (really fast clock !), you could transition in three steps: From rising_edge(clk) to falling_e dge(clk_90), then to falling_edge(clk), and finally to rising_edge(clk_90). Each of these are 3/4 period transfers.

As long as the tool understands the timing relationship between the two rel ated clocks, it will correctly analyze the timing on transfers between them , and report any problems.

Andy

Hi Andy,

Thank you very much for your quick reply.

Frequency of both the clocks are 100Mhz. So data should be stable before

2.5ns - set up time if data is transferred between clk clock to clk_90 clock directly. I am using Quartus II tool for CDC test which report warnings that multiple data bits are transferred asynchronously. I think it can be ignored.

If its not working then I can try other alternatives as you suggested.

Thanking you,

Krupesh

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Hi Andy,

I can successfully transfer data between clk and clk_90 clock without getting any timing violation or CDC warnings.

Thanking you,

Krupesh.

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--------------------------------------- Posted through

Hi Andy,

I can successfully transfer data between clk and clk_90 clock without getting any timing violation or CDC warnings.

Thanking you,

Krupesh.

it

then

each

at

allows

--------------------------------------- Posted through