Using verilog and ISE 10.1.
I add a reg to modify the design's behaviour. It works and it works correctly. The change is intended to invert the carry logic for some op-codes.
However synthesis , using XST , gives the following warning message.
WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
What I would like to do is to find out which lines are caing this warning and see if I have missed something or the synthesis tool has made a mistake.
All sixteen op-codes assign something to borrow. Sometimes true, sometimes inverse and sometimes 0.
I added a KEEP statement to the reg and of course everything was OK. When I added a KEEP statement to each line that assigned to the reg borrow I got the abover warning message.
Is there any synthesis qualifiers which say presevre the nets in this line only?
Thanks for any advice andy.