Hi all,
At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed is 20 times lower than in the bram. I couldn't endure it.
Who knows how to speed up the programming in the ddr sdram?
Please help me. Thank you very much!
Athena
Micron MT46V16M16 is the ddr sdram that I am using.
Athena
"Athena" schrieb im Newsbeitrag news: snipped-for-privacy@webx.sUNCHnE...
enable microblaze caches and try again, if you are not using EDK then you need to implement caches yourself
a poorly designed or badly coupled SDRAM controller can bring very large slowdown into the system,
-- Antti Lukats http://www.xilant.com
do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed is 20 times lower than in the bram. I couldn't endure it.
In addition to Antti's suggestion of enabling caches (absolutely essential), try using Xilinx's new mch_opb_ddr controller, and the CacheLink interfaces. These bypass the OPB bus for CPU memory accesses, and also allow wider cachelines than OPB transactions. We see an instant 2X speedup in real terms on uClinux systems with the MCH caches.
All the info is in the MicroBlaze reference guide. CacheLink is also supported in Base System Builder, I beleive.
There were some issues with the mch_opb_ddr controller in EDK7.1, no doubt fixed in 8.1 but hopefully Xilinx will also release a tactical patch to allow support for 7.1 for the late-adopters - hint hint!
John
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