I'm having trouble getting an IBUFDS to use differential termination, DIFF_TERM = "TRUE". I'm specifying the pads with:
-- more code...
-- Generate components for each bit array_gen : for i in din'high downto din'low generate begin
-- Generate differential ended input buffer diffend_gen : if diff_input_g = '1' generate begin ibufds_inst : IBUFDS generic map ( DIFF_TERM => "TRUE", IOSTANDARD => iostandard_g ) port map ( I => din(i), IB => din_n(i), O => ibuf_out(i) ); end generate diffend_gen;
-- more code .....
When I look at the PAR'ed design I'm noticing despite assigning DIFF_TERM = "TRUE", it's not kept. Note that the above is part of a separate entity i'm instantiating a few times in the top entity. It has a generate statement to create IBUFDS, among other ILOGIC parts, for each bit of my signal. Since I can't get the generic attribute to be assigned in the vhdl, I'm hoping that assigning it in the UCF will work. Unfortunately, I have no idea how to do this with generate statements....
I tried the following, among others... INST "my_iface_inst/array_gen(*).diffend_gen.ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen.diffend_gen.ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen(0).diffend_gen.ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen.diffend_gen.ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen0.diffend_gen.ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen/diffend_gen/ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen(0)/diffend_gen/ibufds_inst" DIFF_TERM = TRUE; INST "my_iface_inst/array_gen0/diffend_gen/ibufds_inst" DIFF_TERM = TRUE;
but I can't get it to translate.
Any ideas? It's driving me bonkers...
Thanks.