How to simulate baud rate generator?

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I've gotten the following code for the baudrate generator from
opencores

I've created a Test Bench Waveform for it from my ISE.

Using single clock, Rising edge, Clock High/Low time as 3, Input setup/
Output Valid delay/ Offset as 0

when i run it in modelsim, I dont get any errors, neither do I get any
waves from baud_x_en or baud_en.

======================
-----------------------------------------------------------------------------
--    Filename:    am_baud_rate_gen.vhd
--
--    Description:
--        a paramatizable baud rate generator
--
--    input a 'high speed' clock, and get out a clock enable of x times
the baud rate, and the baud rate.
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Re: How to simulate baud rate generator?

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Holy crap! - you mean places actually  exist for downloading such trivial
code?
You cannot be THAT interested in FPGA design if you have to download such
stuff as this - I summize that this is not your real vocation as you  cannot
have enough interest to work out such trivia - get a job elsewhere!

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Well wooppee doooo

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LOL - I would have thought no output was a fundamental major error?

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snipped - loadsa copied crap



Re: How to simulate baud rate generator?

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Use this trick, or something like it, so that you can simulate in a
reasonably short time but still have the correct baud rate in synthesis.

function calc_divide_ratio is
variable div_r : real := ( clock_freq_mhz * 1000000.0) /
            ((real(baudrate) * real(over_sample)) );
begin
-- pragma translate off;
    div_r := 16.0;    -- or some other fast baud rate for sim
-- pragma translate on;
        return div_r;
end function calc_divide_ratio;

constant    div_ratio_real     : real       := calc_divide_ratio;

The function detects whether you are in simulation or synthesis, and
initialises the constant to a different value in each case.

Now in simulation you only need to wait 16 clocks per bit.

- Brian


Re: How to simulate baud rate generator?
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hmm

when I set my baudrate to 9600, clock_freq_mhz to 50 and over_sample
to 4,
with simulated clock at 20ns clock period,

the period for baud_x_en is 26060ns
How do I know if the generated baudrate is correct?

putting ur function in,
I get 354ns period for baud_x_en instead, which is around 17.25
clocks ..which isnt exactly 16.

and.. i've no idea what is over_sample for..

Re: How to simulate baud rate generator?
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1 / 9600 = 104.166... microseconds
4x oversampling means baud_x_en should come 4 times every
104.16 microseconds.  So 26.041666... microseconds would
be the exact frequency and 26.06 microseconds is very
close (for 8-bit asynchronous transmission you only need
about 1% clock accuracy).

Without looking through the code (not my job :) I'm not
sure why the closer value of 26.04 microseconds wasn't
used, but as I said 26.06 is close enough (about 700 ppm).

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Strange, A clocked process usually only changes on the clock edge
so it would have to be a multiple of 20 nS...  Where did you
get 354nS?  Is this measures from the simulation waveform?

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Oversampling is for the UART receiver.  This allows the
UART to find the center of a bit time.  4x is usually
a minimum number for the receiver to work reliably.
Modern UARTs usually have 16x oversampling.  I would
suggest finding a paper on UARTs and getting an
understanding of the process involved in receiving
asynchronous data.  It's really not complex and at
some point you may actually enjoy designing your
own UART.

Regards,
Gabor

Re: How to simulate baud rate generator?
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ya... from the simulation waveform


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hmm.. actually i only want to transmit...so 4x should be more than
sufficient right?



Re: How to simulate baud rate generator?

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hmm.. actually i only want to transmit...
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so 4x should be more than
sufficient right?

1x is sufficient for transmit

KJ




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