How to secure distributed IP for Xilinx FPGAs?

I have a customer for whom I have designed an FPGA-based board as well as the FPGA code. The FPGA on this board implements a controller for a device with a proprietary interface. I have an NDA with the device manufacturer which gives me access to the proprietary interface specs, so that I can implement the controller for my customer.

The FPGA code can be divided into the following two categories.

1. Blocks which contain information or details of the proprietary interface.
2. The rest of the code.

I am free to deliver the full code to the customer, as long as no proprietary information is divulged.

It is the intent of the agreement with the device manufacturer for my customer to be able to modify their design as long as they can't modify or see any of the details of the IP code which implements the proprietary interface.

I am using Xilinx ISE 6.3i and XST for my design flow.

QUESTIONS

1. Does XST provide any way to generate a secure netlist?

1. Is there any way to generate a secure netlist in the Xilinx implementation flow, then provide the interface definition and this secure netlist to my customer?

2. Are there other synthesis tools (Synplicity, Exemplar, etc.) that will generate encrypted netlists?

1. Are there general-purpose, third-party, tools for encrypting FPGA-based designs at the source or netlist level?

2. Any other suggestions?

TIA

Urb

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