How to reduce jitter of 30-bit accumulator

What is "acceptable" jitter?

If you want a clock with little jitter, you either need a subdivided clock frequency (50MHz/12587, for instance) where you code a simple counter or you use an external PLL.

The "problem" with NCOs and jitter is that the clock edge will *always* be at your system clock edge. Sometimes it's before your "ideal" clock, sometimes it's after.

If one of your clk_dll resources uses your system clock as input, the CLK0 output can be joined by the CLK90, CLK180, and CLK270 outputs and

- with appropriate BUFGMUX or combinatorial logic, you can select which of 4 phases to use rather than toggling at the CLK0 edge only.

If you can't even do that, all that's left is FPGA techniques that are beyond the scope of most engineering designs (and not very well characterized so the spec limits won't be easy to pin down).

- John_H (who has contemplated a discrete DCM replacement)

is