How to Reduce Interconnects (VDD and VSS)

Even if your design runs very slow, the SDRAM module has high current demands.

Since all the VSS and VDD pins are connected, you still need to connect all the pins on the module. Would you consider it safe to ride in a hot-air balloon where the basket is attached by one small rope? It may be all that's "needed" but things will get nasty at the first stress on that rope. The many VSS and VDD pins are primarily 1) to avoid ground bounce where the large changes in current create a voltage differential between the ground on your board and the ground on your module, and 2) to keep the return currents close to the signals in order to keep crosstalk low - if you have poor return current paths, your signals will crosstalk significantly and your clocks will no longer be monotonic.

Don't try for a single sided board. If you're working with pre-manufactured SDRAM modules that aren't designed for extremely slow slew rates, spend the money and do a *4-layer* board. If you want to design the SDRAMs onto your own board, you have a chance at operation with RIGOROUS design attention to reduce crosstalk and ground bounce effects. It sounds like you don't understand the problems you face so it would take a great deal of learning to start to apply that rigor.

A 4 layer board that connects to a solid ground plane and (mostly) solid power planes will allow a reasonable design without the world falling apart. It's nice to have a board where all the signals are connected but it's even nicer if the board will work when clocked.

Bite the bullet. Spend the money.

- John_H (posting from google at the moment)

Did anyone else miss the message that this is in reply to? I found it using google, but it didn't come down on my newsfeed.

Jeremy

Just out of curiosity John, it seems like you are suggesting designing around your own SDRAM chips is much harder than using a module - while I have used neither, I would think using SDRAM ic's are easier since you can place them better - and I don't see the big issue about SI, its' 100 MHz after all (or 133). I mean, I agree, you shouldn't use

I ask because I'm doing my first design around SDRAM, and now would be a good time to find out how doomed I :)

Regarding the original question however, John answered it well - don't try and cheat by only connecting half the VDD's or whatever. They used multiple VDDs for a reason, and they expect you to make use of that. On a 4-layer board, this wouldn't be a problem if you had planes - but 2 layer, I can see why you want to minimize the pin usage. I think you may waste more money than if you were to just have gone with a 4 layer to start... $140 for 2 pieces isn't that bad, is it?

I didn't really have control over including the original note on google when I replied. My (not always reliable) news reader at work (once my PC was up and running again) showed the origninal message as well.

I generally try to include the pertinent parts of the original post when responding, but posting through google is a different ball of wax.

- John_H

SI is still an issue because it's not the frequency, it's the edge rates. Working with ICs can be easier than working with modules for 1-3 chip designs. The original poster wanted to use a single layer board (?!) which wouldn't support most modern devices' current needs and still maintain any semblence of logic levels.

If you *know* what you're doing, a 2-layer board can work. Decoupling becomes more critical since the VCC impedance will be significantly dependent on the caps and their locations versus the 4-layer board that has a low impedance from many distributed decoupling caps to the chips. If modules are used (my latest experience was DDR-2s) there may be a VCC "region" separate from the grounds requiring decent decoupling between the

SI for a single line can easily be tamed with appropriate termination schemes. A multitude of signals, however, require good terminations *and* good return paths. The larger problem on a 2-layer board may be the bounce provided by poor VCC impedances even if the ground impedance is kept reasonably solid. It's the edges we worry about most, not the frequency.

If you have the experience under your belt to understand what kind of crosstalk and chip-rail related I/O overshoot/undershoot you get with chips that handle the edge rates of your memories, you have a good chance of not being doomed. If you push up to 4 layers to keep solid VCCs and grounds and stay aware of the return paths for your signals (especially your clocks) you should be golden.

The cost of 4 layer boards isn't outrageous these days even in prototype quantities. The headaches from a 2-layer board aren't worth the difference in prototype costs unless you have nothing better to do than enjoy the extra weeks figuring out why your design is flakey (which some people might!)

- John_H

Well put. I'm aware it's all about edge-rates, but not having the Micron datasheet handy, it was easier to fire off the frequency :) Besides, you rarely see a 10 MHz signal with the edge rate typically found in a 10 Gbps signal... at least I haven't! I definitely recommend a thorough 3+ readings of Howard johnson's High-speed digital design - for those interested in SI (just as an aside).

I am definitely using 4-layer for my upcoming design, so return paths shouldn't be a problem. I'm more concerned about how I can't verify the SI on the board since I don't have a scope at all... are simple series-end terminators sufficient for SDRAM, or are more complicated termination schemes advised?

PS: I don't mean to hijack the thread - I just thought since my questions are relevant, and potentially of interest to the poster, I would post here...

Even if you are sure that your final target is 2 layers, it might be better to use 4 on the prototype stage to reduce the risk and get the software guys off the ground and off your back.

Then you can work on making 2 layers work in parallel with software development. And if your new/inexpensive boards crash occasionally when the old/prototype ones don't, the software guys have a good claim that their code is not the problem. (Assuming you didn't make many other changes so you can run the same code.)

Very good advice - and often you can finish the 4 layer design faster, so gain valuable up-front time. You can also probe to find which nets are the really noisy ones, and so need special care on the 2 layer design.

Also, there is nothing quite like this to focus a bean-counters mind : "You can have this one for $Y, that works, or this one, for a saving of ZZc, that fails EMC, and is not as reliable ?" :)

On 2 layer, placing physically small SMD CAPS on the opposite PCB side, right underneath the FPGA, can also buy some trade off.

There are BGA packages especially designed for 2 layer PCBs, so it can be done, but the FPGA vendors currently have other priorities. It may come that they chase lowest applied cost, and target 2 layer applications, and also include caps in their BGA stackups. [ Which is really just a tiny multilayer PCB anyway ]

-jg

Do yourself a favor and buy or rent a scope.

You can get a used Tek 485 scope (350 MHz) for under $500, but 350 MHz isn't really fast enough to fully check SI for a 100 MHz SDRAM interface. Still, it will let you spot gross SI problems.

If your signals are all piont-to-point, source series terminations are great. If your signal traces are under 2", don't bother with the series terminations where the edge slew will be much longer than the round-trip delay and you might get worse performance adding all the vias for the resistors. If you have multiple destinations, the source series terminations might not do you the good you hope they will. If your topology isn't simple, free SI tools for simple simulations appear to be available.

All excellent advice (especially about the scope!)

Putting down chips rather than a stick has pros and cons - on the one hand, it is possible to control the part positioning, but the layout rules (especially length match) become quite complex if there are more than a couple of devices involved.

A stick, on the other hand, has a single interface point (although one must then live with it taking much of the timing budget).

Micron used to have a SDRAM app note with a 4 layer layout which can be an excellent starting point for someone without much experience.

A typical single ended via adds around 0.2 - 0.5dB of frequency dependent loss (at around 500MHz) which will add to deterministic jitter on the signal, so the advice about considering vias is very important.

As already noted, there are a host of things to be considered for successful SDRAM / DDR design. I would strongly suggest reading High Speed Digital Design. A Handbook of Black magic by Howard Johnson if you have not done this type of design before.

Cheers

PeteS

Hey everyone, thanks for the tips! Some follow up questions - I only have the 2 SDRAM (16Mx16) Micron IC's left to route, so I thought I would ask for advice. They are right up against the FPGA (Cyclone EP1C12Q240 - QFP), with the long side against the long side of the FPGA (as opposed to 'standing up') - I was thinking since I can choose pin placement on the FPGA, I could route every other FPGA pin to the side of the RAM facing closest to the FPGA, and then the alternate pins on the bottom layer (4 layer board) under the SDRAM to the side further away from the FPGA. Since it's only a 4-layer, getting decoupling may be tricky with this way, but I'm using 0402's, so it may work. Also, is there a specific FPGA pin I should use for the clock, and should I buffer it? I have 2 modules, one of the top side of the FPGA, one on the bottom, and they aren't sharing any signals. I suppose you could argue that I should share address/control lines to form a x32 bus, but I have the pins to spare and it saves on complexity. I'm not sure if it would be possible on a 4-layer also (or is it?).

Any thoughts?

The critical length match for SDRAM is data, data strobe and clock. Although the address has specific length match rules, the tightest constraints are timing for the data phase.

Without knowing what SDRAM and what speed you are running, I can't give specific advice about routing or routing rules.

Cheers

PeteS

I am using Microns MT48LC16M16A2P-75 part. Trace lengths are well below

woops, I totally forgot the speed - 133 MHz max, but 100 Mhz most likely.

I have to go and do some real work (you know, the stuff that brings in money), but I'll look at the specifics later. One other thing - are you using them in parallel ( so you access data from the devices at the same time) ?

Cheers

PeteS

Thanks for your time Pete, I do appreciate it - as I mentioned, these share no signals, I wanted to keep it simple. I will be combining them to form a 32-bit bus inside the FPGA, but outside, no shared signals.

With that in mind, should I be using special pins for the SDRAM CLK signals? I have never used an SDRAM core, so I don't know what clock it is expecting on the input, and if I should use a special CLK pin on the output. I have 2 oscillators on board that go to the Cyclones PLLs, and one more that goes to a DPCLK pin.

These are pretty much the last thing I have left to route, so any advice will be appreciated!

Hi...again :) First thanks for such a nice response..

As everyone suggested that donot try to use 1 or 2 layer but instea

go for four layer .. but the problem is ... in my country (Pakistan) 4-layer is no available... and as RAM is just a part of my final year projec (Designing of Gaming Console using FPGA) so obviously i donot hav much time to get 4-layer PCB from Abroad M NEE As I need only 1MB to 4MB RAM with a better speed (as also wan to use it as Video RAM :? ) So I also tried to get chips.But here only 32KB is availabl with a worst speed of 85 ns. So for chips I contacted to Micron,s office in China (as no present in my country).But they responded that they send a shipmen of atleast of $500...and I need only one or two SDRAM Chips of 16MB. :D [b:d11e0ac89c][color=darkred:d11e0ac89c]Pleas Suggest[/color:d11e0ac89c][/b:d11e0ac89c [color=darkred:d11e0ac89c]Query_1:-[/color:d11e0ac89c Where to Get a Cheap SDRAM chip (Better if micro as i have done work with it) and also Video RAM .And mor importantly that i need just one or two :( [color=darkred:d11e0ac89c]Query_2:-[/color:d11e0ac89c Where to get cheap 4-layer PCB or some alternativ of it [color=darkred:d11e0ac89c]Query_3:-[/color:d11e0ac89c Major area where i need more RAM (and also it speed) is for Video RAM ,,,,,,,,,,,,suggest how can reduce thi need,,,,,,,,,,,,, :) ,,,,,,,,,,as if reduce it and get manage it on very less.....then ca try to use series of chips......... of RAM

Waiting for Response :

I haven't been following this thread, however it looks like you started out by designing for RAM modules (ie PCBs containing several DRAM chips). It then looks like you decided routing this on 1/2 layer PCB would be too complex so you'd like to go to a 16MB DRAM chip.

I'd recommend that in all cases you will really need a 4 layer board. This is especially true if you've only done a few board designs, and certainly if you've never successfully completed one involving high speed interconnects.

There are many good fast prototype board houses in the US, many will produce 4 layer boards in under a week. So including shipping you could have one in less than 2 weeks. The cost is also quite reasonable, maybe a couple of hundred dollars for a one off.

You could then choose whether you'd prefer to route for a single chip (or maybe a couple) or whether you'd prefer to include a RAM module slot (which is what I'd do based on what the design seems to be for).

If you request some academic samples you may be able to obtain a couple. I've had good experience with Micron in this regards before. Try mentioning what you're after the samples for when you talk to your local distributor. If they're not helpful, try a distributor slightly further afield.

I'm surprised that you only mention issues with routing for your memory modules. Have you had no other routing problems, such as the FPGA -> host etc? 2 layers is really not that much when you've got to include power and ground on them... How are you getting your bitstream to the FPGA?