How to properly use Analyzer, ILA ChipScopePro

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Dear

I need some help on ChipScope Pro.

I implemented simple processing element(PE) and directly connected the
PE with BRAM (RAMB16_S36). Job of this PE is
- to read 4 numbers 3,4,1,2 (each stored in address
0000,0001,0002,0003, respectively) from BRAM.
- sort them.
- store 1 ->2 ->3 ->4 in BRAM (each stored in address
000A,000B,000C,000D)

Both of the functional (Modelsim) and the post-synthesis timing
simulation (Modelsim,XST,ISE6.3i) are okay. Problem is to verify the
design after downloading into the device (V2pro).

Problem is that

In Analyzer, the wavefrom is always "0100", which is the last sorted
number. I am trying possible configuration but I could not see the
waveform "1->2->3->4. I think this is possibly because of the improper
setting in ILA and Analyzer.

If someone helps me with this troubleshooting, it will be appreciated.

Thankyou in advance. Regards.

The configuration for the (ILA,ICON,VIO) core generation is the
following.
------------------------------
* ICON
- 2 control ports
* ILA
- 2 input trigger ports
- Trig0 : 2  bit wide, 1 match unit, basic w/edge type
- Trig1 : 16 bit wide, 1 match unit, basic type
- 4 bit wide data
* VIO
- 1 bit wide asynchronous input
- 7 bit wide asynchronous ouput

* Analyzer
- Match function M0 == R1 , M1 == 000A
- Trigger condition == M0 and M1
- Windows and position=0
------------------------------

------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library UNISIM;
use UNISIM.vcomponents.all;

-- Top Entity
entity PE_MEM_Direct is
port( clk    : in  std_logic;
      sorted : out std_logic  );
end PE_MEM_Direct;

architecture TB_ARCHITECTURE of PE_MEM_Direct is

-------------------------------------------------------------------
--  User Design : Processing element component declaration
-------------------------------------------------------------------
component PE
port(
  en:      in  std_logic; -- PE enable
  clock:   in  std_logic;
  reset:   in  std_logic;
  Din:     in  std_logic_vector(31 downto 0); -- Data input
  ce:      out std_logic; -- Memory chip enable
  r:       out std_logic; -- 'read' memory
  w:       out std_logic; -- 'write' memory
  addr:    out std_logic_vector(15 downto 0); -- Address
  Dout:    out std_logic_vector(31 downto 0); -- Data out
  sorted:  out std_logic  );
end component;

signal T_enPE,T_reset,T_ce,T_r,T_w,T_sorted: std_logic;
signal T_dinPE,T_dout: std_logic_vector(31 downto 0);
signal T_addrPE: std_logic_vector(15 downto 0);


-------------------------------------------------------------------
--  BRAM : component declaration
-------------------------------------------------------------------
component RAMB16_S36
generic (
INIT_00 : BIT_VECTOR
:=X"0000000000000002000000010000000000000000000000000000000400000003"
);
port (
  DO:   out STD_LOGIC_VECTOR (31 downto 0);
  DOP:  out STD_LOGIC_VECTOR (3 downto 0);
  ADDR: in STD_LOGIC_VECTOR (8 downto 0);
  CLK:  in STD_ULOGIC;
  DI:   in STD_LOGIC_VECTOR (31 downto 0);
  DIP:  in STD_LOGIC_VECTOR (3 downto 0);
  EN:   in STD_ULOGIC;
  SSR:  in STD_ULOGIC;
  WE:   in STD_ULOGIC);
end component;


signal T_we,T_enMem,T_ssr: std_logic;
signal T_addrMem: std_logic_vector(8 downto 0);
signal T_dinMem,T_DO: std_logic_vector(31 downto 0);
signal T_dip,T_dop: std_logic_vector(3 downto 0);

-------------------------------------------------------------------
--  ICON core component declaration
-------------------------------------------------------------------
component icon
port
  ( control0    :   out std_logic_vector(35 downto 0);
    control1    :   out std_logic_vector(35 downto 0) );
end component;


------------------------------------------------------------------
--  ICON core signal declarations
-------------------------------------------------------------------
signal control0       : std_logic_vector(35 downto 0);
signal control1       : std_logic_vector(35 downto 0);

-------------------------------------------------------------------
--  ILA core component declaration
-------------------------------------------------------------------
component ila
port
( control     : in    std_logic_vector(35 downto 0);
  clk         : in    std_logic;
  data        : in    std_logic_vector(3 downto 0);
  trig0       : in    std_logic_vector(1 downto 0);
  trig1       : in    std_logic_vector(15 downto 0)  );
end component;

-------------------------------------------------------------------
--  ILA core signal declarations
------------------------------------------------------------------
signal data       : std_logic_vector(3 downto 0);
signal trig0      : std_logic_vector(1 downto 0);
signal trig1      : std_logic_vector(15 downto 0);

-------------------------------------------------------------------
--  VIO core component declaration
-------------------------------------------------------------------
component vio
port
( control     : in    std_logic_vector(35 downto 0);
  async_in    : in    std_logic_vector(0 downto 0);
  async_out   : out std_logic_vector(6 downto 0) );
end component;

-------------------------------------------------------------------
--  VIO core signal declarations
-------------------------------------------------------------------
signal async_in   : std_logic_vector(0 downto 0);
signal async_out  : std_logic_vector(6 downto 0);


begin

-------------------------------------------------------------------
--  User Design and BRAM instantiation
-------------------------------------------------------------------
 UUT : PE  port map
(T_enPE, clk, T_reset, T_dinPE, T_ce, T_r, T_w, T_addrPE, T_dout,
T_sorted);

 R1 : RAMB16_S36 port map
(T_DO, T_dop, T_addrMem, clk, T_dinMem, T_dip, T_enMem, T_ssr, T_we);


-------------------------------------------------------------------
--  Interface logic between PE and BRAM
-------------------------------------------------------------------

sorted <= T_sorted; -- connection between memory and processor
T_dinPE <= T_DO;
T_enMem <= T_ce;
T_addrMem <= T_addrPE(8 downto 0);
T_dinMem <= T_dout;

process(T_ce,T_r,T_w)
begin
  if T_ce='1' and T_w='1' and T_r='0' then
     T_we <= '1';
  else T_we <='0';
  end if;
end process;

-------------------------------------------------------------------
--  ICON core instance
-------------------------------------------------------------------
i_icon : icon
port map
( control0    => control0,
  control1    => control1  );

-------------------------------------------------------------------
--  ILA core instance
-------------------------------------------------------------------
-- Trigger signals
trig0(0) <= T_ce;      -- Memory chip enable
trig0(1) <= T_w;       -- Write

-- Address bus (16 bit)
trig1(0)  <= T_addrPE(0);
trig1(1)  <= T_addrPE(1);
trig1(2)  <= T_addrPE(2);
trig1(3)  <= T_addrPE(3);
trig1(4)  <= T_addrPE(4);
trig1(5)  <= T_addrPE(5);
trig1(6)  <= T_addrPE(6);
trig1(7)  <= T_addrPE(7);
trig1(8)  <= T_addrPE(8);
trig1(9)  <= T_addrPE(9);
trig1(10) <= T_addrPE(10);
trig1(11) <= T_addrPE(11);
trig1(12) <= T_addrPE(12);
trig1(13) <= T_addrPE(13);
trig1(14) <= T_addrPE(14);
trig1(15) <= T_addrPE(15);

-- Data capture
data(0) <= T_dout(0);
data(1) <= T_dout(1);
data(2) <= T_dout(2);
data(3) <= T_dout(3);

i_ila : ila
port map
( control   => control0,
  clk       => clk,
  data      => data,
  trig0     => trig0,
  trig1     => trig1   );

-------------------------------------------------------------------
--  VIO core instance
-------------------------------------------------------------------
-- 7 outputs for VIO :
process(async_out)
begin
  T_enPE    <= async_out(0);
  T_reset   <= async_out(1);
  T_ssr     <= async_out(2);
  T_dip(0)  <= async_out(3);
  T_dip(1)  <= async_out(4);
  T_dip(2)  <= async_out(5);
  T_dip(3)  <= async_out(6);
end process;

-- This is the way I drive the internal signal
async_out(0) <= '1';    -- 'en'
async_out(1) <= '0';    -- 'reset'
async_out(2) <= '0';    -- 'ssr'
async_out(3) <= '1';    -- 'dip(0)'
async_out(4) <= '1';    -- 'dip(1)'
async_out(5) <= '1';    -- 'dip(2)'
async_out(6) <= '1';    -- 'dip(3)'

---- 1 Input for VIO
async_in(0) <= T_dout(0);

i_vio : vio
port map
( control   => control1,
  async_in  => async_in,
  async_out => async_out  );
 
end TB_ARCHITECTURE;


Site Timeline