Dear
I need some help on ChipScope Pro.
I implemented simple processing element(PE) and directly connected the PE with BRAM (RAMB16_S36). Job of this PE is
- to read 4 numbers 3,4,1,2 (each stored in address
0000,0001,0002,0003, respectively) from BRAM.- sort them.
- store 1 ->2 ->3 ->4 in BRAM (each stored in address
000A,000B,000C,000D)Both of the functional (Modelsim) and the post-synthesis timing simulation (Modelsim,XST,ISE6.3i) are okay. Problem is to verify the design after downloading into the device (V2pro).
Problem is that
In Analyzer, the wavefrom is always "0100", which is the last sorted number. I am trying possible configuration but I could not see the waveform "1->2->3->4. I think this is possibly because of the improper setting in ILA and Analyzer.
If someone helps me with this troubleshooting, it will be appreciated.
Thankyou in advance. Regards.
The configuration for the (ILA,ICON,VIO) core generation is the following.
------------------------------
- ICON
- 2 control ports
- ILA
- 2 input trigger ports
- Trig0 : 2 bit wide, 1 match unit, basic w/edge type
- Trig1 : 16 bit wide, 1 match unit, basic type
- 4 bit wide data
- VIO
- 1 bit wide asynchronous input
- 7 bit wide asynchronous ouput
- Analyzer
- Match function M0 == R1 , M1 == 000A
- Trigger condition == M0 and M1
- Windows and position=0
------------------------------
------------------------------------------------------------ library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;
library UNISIM; use UNISIM.vcomponents.all;
-- Top Entity entity PE_MEM_Direct is port( clk : in std_logic; sorted : out std_logic ); end PE_MEM_Direct;
architecture TB_ARCHITECTURE of PE_MEM_Direct is
-------------------------------------------------------------------
-- User Design : Processing element component declaration
------------------------------------------------------------------- component PE port( en: in std_logic; -- PE enable clock: in std_logic; reset: in std_logic; Din: in std_logic_vector(31 downto 0); -- Data input ce: out std_logic; -- Memory chip enable r: out std_logic; -- 'read' memory w: out std_logic; -- 'write' memory addr: out std_logic_vector(15 downto 0); -- Address Dout: out std_logic_vector(31 downto 0); -- Data out sorted: out std_logic ); end component;
signal T_enPE,T_reset,T_ce,T_r,T_w,T_sorted: std_logic; signal T_dinPE,T_dout: std_logic_vector(31 downto 0); signal T_addrPE: std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- BRAM : component declaration
------------------------------------------------------------------- component RAMB16_S36 generic ( INIT_00 : BIT_VECTOR :=X"0000000000000002000000010000000000000000000000000000000400000003" ); port ( DO: out STD_LOGIC_VECTOR (31 downto 0); DOP: out STD_LOGIC_VECTOR (3 downto 0); ADDR: in STD_LOGIC_VECTOR (8 downto 0); CLK: in STD_ULOGIC; DI: in STD_LOGIC_VECTOR (31 downto 0); DIP: in STD_LOGIC_VECTOR (3 downto 0); EN: in STD_ULOGIC; SSR: in STD_ULOGIC; WE: in STD_ULOGIC); end component;
signal T_we,T_enMem,T_ssr: std_logic; signal T_addrMem: std_logic_vector(8 downto 0); signal T_dinMem,T_DO: std_logic_vector(31 downto 0); signal T_dip,T_dop: std_logic_vector(3 downto 0);
-------------------------------------------------------------------
-- ICON core component declaration
------------------------------------------------------------------- component icon port ( control0 : out std_logic_vector(35 downto 0); control1 : out std_logic_vector(35 downto 0) ); end component;
------------------------------------------------------------------
-- ICON core signal declarations
------------------------------------------------------------------- signal control0 : std_logic_vector(35 downto 0); signal control1 : std_logic_vector(35 downto 0);
-------------------------------------------------------------------
-- ILA core component declaration
------------------------------------------------------------------- component ila port ( control : in std_logic_vector(35 downto 0); clk : in std_logic; data : in std_logic_vector(3 downto 0); trig0 : in std_logic_vector(1 downto 0); trig1 : in std_logic_vector(15 downto 0) ); end component;
-------------------------------------------------------------------
-- ILA core signal declarations
------------------------------------------------------------------ signal data : std_logic_vector(3 downto 0); signal trig0 : std_logic_vector(1 downto 0); signal trig1 : std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- VIO core component declaration
------------------------------------------------------------------- component vio port ( control : in std_logic_vector(35 downto 0); async_in : in std_logic_vector(0 downto 0); async_out : out std_logic_vector(6 downto 0) ); end component;
-------------------------------------------------------------------
-- VIO core signal declarations
------------------------------------------------------------------- signal async_in : std_logic_vector(0 downto 0); signal async_out : std_logic_vector(6 downto 0);
begin
-------------------------------------------------------------------
-- User Design and BRAM instantiation
------------------------------------------------------------------- UUT : PE port map (T_enPE, clk, T_reset, T_dinPE, T_ce, T_r, T_w, T_addrPE, T_dout, T_sorted);
R1 : RAMB16_S36 port map (T_DO, T_dop, T_addrMem, clk, T_dinMem, T_dip, T_enMem, T_ssr, T_we);
-------------------------------------------------------------------
-- Interface logic between PE and BRAM
-------------------------------------------------------------------
sorted