Hi all,
I tried to find the information in Xilinx documentation and Internet with no luck. I come here as my last resort.
My design fails to meet all constraints, and throws the following message:
"WARNING:Route - CLK Net:dsp_clk_a_IBUFG may have excessive skew because 685 CLK pins and 1 NON_CLK pins failed to route using a CLK template."
As far as I am concerned, this can be due to the clock signal (dsp_clk_a) feeding a non-clk input. The problem is that I cannot find the non-clk element. The only one I can figure out is a BUFGMUX with 2 inputs: dsp_clk_a and GND, and it's output to an output PAD of the FPGA. This BUFGMUX is supposed to export a clock signal only when desired, leaving the clock inactive when not.
Can anyone tell me if this BUFGMUX can be the problem, or how can I find the non-clk element?
Thanks a lot. JL.