hi
I need to measure "number of clock cycles" or "execution time", after mapping the VHDL code into Vertex II pro.
In Modelsim simulation, it took 350 cycles with 20 MHz clock frequency. I hope the performance after the mapping will be same as the performance in simulation.
In ISE 6.3 (or EDK 6.3) , how can we measure the amount of clock cycles?
Maybe I can use "big" counter along with my design. Are there any efficient way to do so?
Thanx
Your hopes should be well founded. Assuming your design is fully-synchronous, and the timing analyser says it meets your 20MHz clock spec, the design will work as it does in simulation.
You don't need to.
Cheers, Martin
-- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
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