Some of the xilinx fpga pins are wired to leds. P39 for instance is wired in such a way. In my design I have a vhdl counter and want to direct ISE (v.6.3i) to tie the output of the counter to P39. What is the way to do this?
It seems that PACE does this, but then Floorplanner and FPGA Editor seem to do something similar to this as well. When I tried to use PACE, I saw I could specify the Loc as "BANK6", but could not figure out how to directly assign to the pin #. In Floorplanner I could select File->Read Constraints..., but wasn't sure this would do what I wanted either.
In Xilinx ECS I could create a schematic that wires together the vhdl counter. It occurs to me that this is also a possible place to assign the output to P39. Is that true?
Thanks,
-beagle