Hello everybody, I use FPGA Advantage 6.2 and ISE Xilinx 7.1. Is there some tool that allows for the verification of the content of a block RAM (RAMB4_x_y) at simulation time, but without having to increase step by step the address and monitoring the output DOA? That is some graphical interface that give a view of a selected RAM cell Thanks Gio
Are you using Modelsim ?
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The simulation models for block RAMs use an array to store memory content. You can view the content of the array like you view any other variables.
Jim
Yes I'm using Modelsim, is there some way to do that with this tool? I tried to perform a behavioral simulation, but I don't know how to check the memory (I'm not able to check it with the wave pane because the DIA is generated during the simulation). Thanks a lot Giovanni
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