How to keep the design from Synplify or XST optimizing

Hi, I have a problem that after Synplify or XST optimizing, my 16x8 RAM is reduced to 1x8. This is not my hope. How to avoid this?

Reply to
zephyrer
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hi, as far as i know this is because u r not using those RAMs (the synthesize tools will optimize those are not using in your design). to remove such optimisation u can untick the options in the synthesize(properties) like register duplication and equvalent register removal.

Reply to
subin

Search the keyword "keep" or "preserve" in the tool manuals and go from there.

HTH, Jim

Reply to
Jim Wu

One silly idea: check your address register to make sure it's defined as a

4-bit value, not a single bit register. I sometimes forget my dimensions in the definitions.
Reply to
John_H

thank u for ur tips,the synthesis command "syn_keep" "syn_noprune" and "syn_preserve" can prevent instances or reg or wire from optimizing. Now I hope to keep the net connections and stop optimizing the whole design, fit the design to a FPGA, is there any solution?

Reply to
zephyrer

You can also use syn_hier ="hard" for Xilinx in synplicity to force it to respect the component boundaries so that it doesn't share stuff between hierarchical components.

Reply to
Ray Andraka

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