Hi everyone, I have a VHDL file which I use it in EDK in one of my custom cores ..I also have a netlist file which has been generated using JHDL . The netlist file is in EDIF format. So now i want to import this netlist file in my VHDL so that I can connect to the JHDL component .I dunno if this is actually feasible to do . In case anyone has done this sort of stuff ..Help me out guys!!
Thanks in advance
-- Parag
I have never done it myself but I believe that if you go to Tools->Create/Import Peripheral Wizard you can choose to import a peripheral and a few windows later it will allow you to direct it to the netlist files that compose your core.
To do this in ISE, I believe you can use the Core Generator. For more info check this Xilinx Answer record
Hope this helps
Robin
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