How to implement this C function in FPGA

What exactly is this problem solving?

I assume that any use of Matlab implies DSP at more mundane precision levels ie single precision.

You haven't mentioned what performance requirement you have, how many doubles FP ops/sec.

It looks like if you could do this at all in an FPGA you will be needing a big one or will settle for many cycles.

If its low I might have said MicroBlaze with a single precision FPU.

You could design your own FPU free of the complexities of IEEE, when I

1st leart FP, it was tought as something straight forward, now its all magic.

You could perhaps use block floating point, or use differnet number systems.

regards

johnjakson at usa dot com

Hi John,

Thanks for your feedfack.

Using the FPGA to compute this function instead of CPU.

There is no performance requirement for my concern, as long as the function is evaluate from the FPGA instead of CPU.

needing a big one or will settle for many cycles. Size of logic gates that it consumed is also not a matter.

Thanks for given this information, but I don't know to implement this onto a FPGA, what is the best way that I can get start with designing this FPU?

systems. But normally the floating point IP block doesn't have trigonometric function

Kindest regards,

Stanley

Yes, but why are you moving this from a CPU to and FPGA ???

So it isn't for speed.

You aren't doing it for cost.

You don't know how to implement floating point in an FPGA.

You dont know the difference between block floating point and a floating point block.

I'll bet you don't know how to do trig with basic floating point either.

I'll guess (based on your posting domain) that you are prototyping an ASIC. Therefore, getting this to run on an FPGA is probably the least of your problems. You need to figure out how this is going to run on your ASIC. Then write the HDL. Then simulate it. Then maybe port it to the FPGA (if it will fit), or multiple FPGAs.

Good luck, Philip

(FYI, my response to your initial post was to run screaming from the room, waving my hands wildly in the air. I could not think of a good way to post that.)

I wish you even more good luck.

Philip Freidin Fliptronics

Stanley

Since you are not going to or are not able to disclose any details about the project, you probably won't get any real help here, I think I understand your situation. You only got a response because of your tsmc address.

Its a shame you didn't post 2 months ago, I was in Hsinchu for some time, I could of just walked in signed the NDA and worked out a consultancy deal for you and given you a few months of my time. My wife certainly wouldn't have minded staying longer.

I and many others here are used to working on wierd and or interesting problems for US/EU hourly rates though.

As a former customer of TSMC foundry services on a wavelet chip that also turned some neat FP math into integer ASIC, I understand that your group might not want the world to have a clue what you might be up to after all you are supposed to be a pure play foundry. This project does not fit what I usually see designed in Taiwan (thinking mobo, networking, controllers, consumer etc).

You can write me or any of the regular consultants here if you want some serious help.

regards

johnjakson at usa dot com

508 480 0777

Please explain what you are really trying to do.

One reason to use FPGA instead of a more traditional processor is speed. An FPGA can do many additions, and with newer models, many multiplications at the same time. If your algorithm can be parallelized that way it can run much faster in an FPGA.

For this to make sense, though, there must be a real need for the speed, especially when floating point is involved.

In an FPGA the barrel shifters required to do floating point addition (pre and post normalization) is much larger than the logic that does the actual addition. For multiply it isn't so bad with integer multiply hardware. Division is a lot of work, fixed or floating point.

If you don't need speed then it isn't so hard to do in an FPGA, but it is even easier in a normal processor.

For your problem it might be that 60 bit fixed point will do. It might also be that you can use fixed point with the binary point at different positions in different parts of the calculation.

To really answer the question the real goals of the project need to be considered, including cost, development time, and speed of the final product. (Both delay and throughput.)

-- glen

I am product manager at AccelChip, one of the tools mentioned by Stanley earlier in the thread. As he notes, our tool is primarily intended for algorithms beginning in MATLAB. Typically our customers would have an algorithm such as this in MATLAB. A benefit of MATLAB is that there are preexisting functions such as polyval() that perform functions like polynomials in one variable quite compactly.

Tools like AccelChip and System Generator have generally presumed the design will be put into fixed-point form which has numerous advantages over floating point. The trick is determining how much precision is truly required and this ultimately takes knowledge of the design and its system requirements. It's not immediately clear to me how much precision you will require, but 7 decimal places in fixed-point is about 23 bits which is well within the precision ranges of these tools.

Best regards,

--Eric

Hi,

MicroBlaze has now an optional integrated single precision FPU. Depending on your performance and precision needs this might help you tremendously.

You only need to enable the FPU in MicroBlaze and compile your C code.

Göran

Stanley wrote: