how to implement a good register decoding logic

Hi all, Alreay asked a few questions on this issue.. the problem is i want to implement a register read logic input is from

20 4bit registers and the output is 10 4bit wide bus. Each 4 bit element at the output can take values from any of the registers. I have implemented this with a simple indexing in the verilog like for (i=0 to 9) out[i] = reg[index[i]]; This is implimented as mux. But i want to know is there any better way to do this. I am working on the virtex E processor. What will happen if i implement this decodeing by using the RAM. That is to create a 20bit x 10 RAM and AND the RAM output with the register bit and then OR it together. Will that save area considerably. I think no. but i just want to know all of your expert openions on this. Also i am wondering which coding style will be suited for the ASIC migration (no experiance in that). Please comment on this. regards Sumesh V S