how to immitate clock behavior----Please guide

Have you simulated this design? The xilinx tools come with a free version of Modelsim(a simulator). Write a testbench in VHDL/verilog to generate stimulus for your design, then have a look in the waveform window to see if the outputs and internal signals are as you were expecting.

Using a switch as a clock is like lending your wife the credit card. Anything could happen. Get a scope and have a look at the switch output when you press the switch. Most likely you will see it glitch up and down quickly as you depress the switch.

Get it working in the simulator first, then think about getting it to work on real hardware.

Manpreet schrieb:

synthesis but is having like 100 warnings of some ports being disconnected.

FPGA Spartan stater kit not working?

nothing toggling. I used LEDS for O/Ps and switches for Inputs. But, i have Locked one switch for CLOCK on the kit itself and try to toggle the clock by hand.

mismatch and low frequency.

clock to see the outputs.

Hi Preet,

have you provided any debouncing circuitry for your clock (and inputs)? Otherwise, every press and release of the clock button results in an unknown number of clock pulses. (Keep in mind that a debouncing circuit needs to be clocked with less than 100 Hz!)

For the disconnected ports: Do a simulation! Does it work? Do the outputs toggle? Check your synthesis report. Is there a warning about some signals (preferably Enables) becoming tied to VCC or GND? This causes XST to eliminate the following circuits for their outputs will remain constant as well. And because the other inputs of these circuits are not used anymore they become disconnected.

Do you feed the clock into a DLL/DCM? This might not work with a manual clock. At least DLLs need a minimum Clock frequency!

Have a nice synthesis Eilert