I implement the design using xilinx device, and one net has high fanout, so I duplicate the register, but it does not work, the net fanout remains the same.
The original code is:
process(clk) begin if clk'event and clk = '1' then regenr
Is the regenr and the regenr2 have the diffient load, or I think you can set the maxfan attribute in your hdl sourse file?For example(verilog) reg regenr /*synthesis syn_maxfan=32*/;//32 is the max fanout that for example you can add yours instead than the synthesis tools will auto duplicate the registers.also you can set the maxfan for all in the synthesis tool,you can look the synplify online help. Best regrads!
=> The synthesis tool gives you a hint, that using a (manually inferred) buffer may be not a bad idea. What buffers are available strongly depends on the target architecture. Sometimes the synthesis tool will infer such buffers automatically, if needed.
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regenr and regenr2 are equal for the synthesis tool.
If you have a synchronous design everything should be done automatically, because the synthesis tool estimates the delay of the high-fanout net, infers the appropriate logic and reports the resulting clock frequency. Because of this high-fanout net the frequency may not be very high. (So the warning is a hint for you to search for the reason for the low frequency.)
Constraining the clock is the most important thing you need to do.
Ralf
I Got the answer. I have add an attribute of equivalent_register_removal to "no" to forbidden ISE to remove the maunally duplicated register. and the fanout decreases.
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