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How to handle the "gate count" issue?

Hi all,

I need some advice on how to treat the "equivalent gate count" issue. I have to make a presentation on something soon, where FPGAs are the initial foundation of the project, and I anticipate having to provide some correlation between "slices" and "gates" as an estimate to the capacity of current-generation FPGAs.

Ideally I would provide a slice and logic area estimate for the specific design, but the design is not nearly complete enough to provide such reliable estimates. For now, I have to arm-wave it. I don't need it to be vendor-neutral though, I can be Xilinx specific. Any suggestions anyone?

-int

Reply to
int19h
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Unless you compare two related FPGA devices, gate count will be rather meaningless, since it is interpreted differently by the ASICand FPGA communities. I would elaborate on: Flip-flop count, I/O count (including required standards including bidirectional LVDS,) gigabit serial I/O. on-chip memory (width and depth), multipliers/accumulators, potential need for an on-chip microcontroller. Those six items should quantify almost any design. Peter Alfke, Xilinx

Reply to
Peter Alfke

Usually I will temper the use of "gates" by saying equivalency can be a factor of x2 or x 1/2 out. A better FPGA metric for Xilinx and Altera is number of LUTs and Flops but even here there are things to muddy the comparision. The technologies that are not SRAM based also don't compare easily on these metrics.

John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 PCI-E Development Board.

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Reply to
John Adair

That seems like a very reasonable approach. Thanks Peter.

Reply to
int19h

yep, a reasonable approach to writing your proposal to be X vendor locked.

Your customer may not be high enough up the food chain to get delivery of the product in a shortage, and doing a design specifically including sole sourced technology that goes on allocation is called Chapter 7.

First, consider each of these functions carefully, are they a MUST HAVE for the product, and if so are there two vendors with parts that fit the bill. If they are MUST HAVE, do they need to be on chip ... would a multi-device design be safer for the product. Is the talent to actually complete the project inhouse already, or is it a specialized field that you may not be able to hire to meet schedule.

The basic question about FPGA's, is there enough LUT/FF's to realize the design. Everything past that, needs to be carefully considered in regards to multi-source availablity should there be high demand and allocation for the parts.

Reply to
fpga_toys

Since you don't mind being Xilinx specific, the following link:

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may be of some help, as it allows comparisons of different devices, and different product families, it does not have the insane Xilinx logic cell inflation factor, it gives the formulas for converting from LUTs/FFs to vendor neutral "Dog Gates" (sort of like Dog Years :-) .

Philip

=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for

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Reply to
Philip Freidin

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