Hi all, I am trying to generate a vcd file from the model sim V6.0a. tried the following command vcd file test1.vcd vcd add -ports /top_module/DUT/*
It is giving all the signals but bus signals are split into separate bits. How can i genrate a vcd file in which bus signals are combined (values in hex) rather than bits.
Also in the documentation of model sim i only found the way to gnerate the vcd file from console. Is there any way to generate that from GUI. Thanks in advance
Hi there,
As far as I know (and I may be wrong, though I've never really investigated this) getting a vcd file with bus value changes instead of individual bit changes isn't possible. Check the modelsim documentation to be sure...
You could write a program to parse the VCD file and translate individual bit changes into changes on a bus. Parsing the file isn't difficult, but if you're in a hurry this might not be the best way to spend your time!
As for an option in the GUI in modelsim to generate vcd files, I've not seen one either... You may find that the FPGA vendor tools you are using will do this for you though - I think there's an option in Xilinx ISE to generate a ".do" file for modelsim with the vcd stuff included.
Sorry I haven't been very specific, but I hope that's useful. Jon
Thank yo very much john for the replay.... I agree with your findings. I wrote a program which converts individual bits to hex values.... Also there is no GUI to genrate vcd file in the model sim.
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