Hi, I would like to ask for your help with a problem I met in simulation with ModelSim.
I generated single port distributed ram with initial file *.mif successfully with Xilinx chip Vertex II.
When I started debugging the design, I found all single port distributed ram were not initialized. All their outputs are 'X'.
I changed my design to make its inputs signal are constant, the results are still 'X'.
I changed initial file name and when running ModelSim it showed errors. It shows ModelSim reads the initial file.
What should I do with ModelSim single port distributed ram initial file problem?
Thank you.
Weng