How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim

Hi, I would like to ask for your help with a problem I met in simulation with ModelSim.

I generated single port distributed ram with initial file *.mif successfully with Xilinx chip Vertex II.

When I started debugging the design, I found all single port distributed ram were not initialized. All their outputs are 'X'.

I changed my design to make its inputs signal are constant, the results are still 'X'.

I changed initial file name and when running ModelSim it showed errors. It shows ModelSim reads the initial file.

What should I do with ModelSim single port distributed ram initial file problem?

Thank you.

Weng

Reply to
Weng Tianxiang
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That is normal for a RAM model. To make a RAM output valid the testbench must perform a write and read cycle to the same address. Maybe a ROM is what you want.

-- Mike Treseler

Reply to
Mike Treseler

Hi Mike, I disagree with your opinion this time.

The reason is there is a *.mif file included in the *.vhd file to be used in initial file for simulation.

Thank you.

Weng

Reply to
Weng Tianxiang

You can also initialize manually the BRAM memory. Use the Language Templates through the ISE to see the way!

Reply to
Vangelis

through the ISE to see the way!

Yes.

Actually I can do it by adding some loops in nRESET = '0' statement to get all signle-port ram initialized, but it is not the same as FPGA situation.

Weng

Reply to
Weng Tianxiang

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