How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4

Hello Peter, thanks... could you tell me where it is documented? I remember that vaguely from the Virtex(2?) days, but can't remember the details. Also, but when I tried to verify that using core generator (I normally instantiate DCM manually instead of using coregen, btw), it says

"The specified input clock frequency restricts your output frequency to LOW frequency range. Either change your input clock frequency or your M/D value to correct this."

Is it a tool issue?

Thanks again.

Click on the Virtex-4 User Guide

1. > >

After answering you from memory, I studied the data sheet more carefully:

You need to be in High Frequency Mode, where you can generate Fx output frequencies between 210 and 300 MHz, as shown on page 35 at the top. One inch further down, there is a Fmin spec of 50 MHz which you can ignore. It was put in there as a precaution against excessive jitter on the input. Hopefully, your clock does not have excessive jitter. Peter Alfke

Guide

Peter - thanks again.

So, I can use 30mhz CLKIN to create CLKFX @240mhz (M=8,D=1)... but can I use CLKFB to remove the insertion delay here? All documents I looked at talk about CLKIN out of the range _and_ using only FX outputs (with no CLKFB hooked up). I can see why that's the case.

If that's the case, how do I receive the 240Mhz data that's synchronous to the 30Mhz input clock

- the delay from the pad thru ibufg, dcm, bufg is not quantified, I don't believe. I wouldn't know how to align the clock to the data. (In the lab, I can, but not over temp, volt, etc...) I mentioned receiving the data in the original post, maybe it got missed.

In addition to Peter comments, you might want to read XAPP265 (High- Speed Data Serialization and Deserialization, 840 Mb/s LVDS).

Patrick