How to get 1.8432 MHz out of 24 MHz with Sparten-3?

Hello

I'm using a Spartan-3. I'm wondering if there is an easy way to fabricate a clock with 1.8432 MHz from a 24 MHz input clock?

Could I use a DCM to get this exact clock frequency?

Or should I make a frequency that over a period of time has an average of 1.8432 MHz?

Reply to
Elektro
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Is divide by 13 not close enough...? 1.8461 would be close enough for RS232 comms

Reply to
Mike Harrison

The answer is that you don't need 1.8432MHz. I assume you use that clock speed for your UART. Just adjust the register of divider in your UART, and it should be able to run with other clock speeds that can be easily derived from the 24MHz crystal.

vax, 9000

Reply to
vax, 9000

240000 / 18432 = 625 / 48

How about a 10-bit register that decrements by 48 every clock tick. Whenever it goes negative, add 625 as well and output a UART clock pulse. Alternatively, if the last clock tick sent it negative, add (625-48)= 577 on the next.

I think this should give the exact average frequency, with a little jitter (edges may vary by one 24MHz clock period.

Reply to
Kryten

I'm not using it for an UART. It's used for an ADS1251 AD-converter to get an exact sampling frequency of 4800 Hz.

But now I got some new ideas, thanks :-)

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Reply to
Mr M

What do you mean by "exact"? How good is the crystal you are starting with?

24 MHz divided by 5000 gives a nice clean 4800 HZ. Why go through 1.8432 MHz?

Another way to look at things... To go from 1.8432 to 4800 Hz, you divide by 384 To go from 24 MHz to 4800 Hz, you divide by 5000 The factors of 384 are: 2 2 2 2 2 2 2 3 The factors of 5000 are: 2 2 2 5 5 5 5 You are going to have troubles going through 1.8432 on the way from 24 MHz to 4800 Hz.

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Reply to
Hal Murray

I'd guess the ADS1251 starts with that ?

So there are a couple of choices

a) Divide by 13, and accept the slight sample error, but zero jitter, or b) divide by 625/48 as someone else suggested.

However, rather than implement split adders as counters, this can also be done with a much simpler swallow counter :

for 47/48 times divide by 13, and for 1/48 times, divide by 14.

Result is 625 clocks in, for 48 out. Freq average is exact, but has slight edge jitter on the /14 cases

-jg

Reply to
Jim Granville

... even simpler to use a script that writes the HDL for you. (This way, there is no chance of making an error.)

formatting link

BTW, "slight edge jitter" is 41ns p-p.

Regards, Allan

Reply to
Allan Herriman

Thank you all. I made a 625/96 divider and toggled the clock output bit by that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks in.

Others than me selected this "odd" frequency, so I couldn't select a more appropriate one by myself. :-/ Otherwise I would have selected another frequency.

And by the way, does anybody know a good book with these kinds of examples?

Thanks :-)

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Reply to
Elektro

Are you aware of the effects of clock jitter on ADC performance? You should check with your system designers about this effect, otherwise you may get "sub-optimal" results, i.e. it won't work.

The ADS1251 is a 24 bit ADC. Assuming a full scale input signal of 1000Hz (a guess, based on Fs =

4800Hz), 41ns p-p of clock jitter will degrade the performance to about 12 bits. This gets better as the input frequency is reduced, e.g. a 100Hz input will give about 15-16 bits. (I made some assumptions that may not apply to Sigma-Delta ADCs though. Unfortunately, the ADS1251 data sheet does not mention its sensitivity to jitter.)

It's possible that the divide by 13 counter would be better, as it generates no jitter. Can you tolerate the frequency error?

Regards, Allan

Reply to
Allan Herriman

Hi All, Just a wild guess here, but would it be possible to increase the 24MHz using a DCM by 2x of 4x, and then using this faster clock to generate the 1.8...MHz signal. The clock period would be smaller, and thus, I assume you could reduce the edge jitter using this fact? Just an idea..haven't given it a lot of thought!

Allan Herriman wrote:

Reply to
John McGrath

[snip]

If you can't live with either 41 ns jitter or the frequency error you could cascade two DCM's using 8/25 and 6/25 respectively for CLKFX_MULTIPLY/CLKFX_DIVIDE. The intermediate frequency would be

7.68 MHz. which is well below the output frequency specification for CLKFX even in low frequency mode, so you'll need to really set the first CLKFX_DIVIDE to 1 and then externally divide by 5 to generate the input to the second DCM. I don't have enough experience with Spartan 3 to tell you how much jitter you will get this way, but if the second DCM actually locks, I can't believe it's anywhere near 41 ns.
Reply to
Gabor

Hello again

I solved it now. I used two DCM's and two dividers.

I set the first DCM to 24/5 then an external 1/10 then the second DCM set to

24/5 and last an external 1/20 :-)

So the output frequency is:

24MHz x (16/5) x (1/10) x (24/5) x (1/20) = 24 MHz x (48/625) = 1843200 Hz

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Reply to
Elektro

I suggest a better distribution: first DCM: 16/5 second DCM: 24/25 final divider by 40 or 16/20 followed by 24/25 followed by divide by 10.

Peter Alfke

Reply to
Peter Alfke

I cant have 16/20 in the first, the output from a DCM must be 24 MHz or greater.

I found another one that works:

first DCM 32/25 second DCM: 21/25 and a last division by 14 I suggest a better distribution:

Reply to
Elektro

I would use a 32-bit accumulator (or a dds) clocked at 24MHz with a constant input of 1.8432*2^32/24. The msb of the output is your clock. Anyone please correct me if I'm wrong.

dsp novice.

Reply to
novice

You will generate the correct average frequency, but with a deterministic jitter of a 24 MHz clock period = 42 ns, which may be objectionable. BTW, your method is called Direct Digital Synthesis (DDS), and you can explain it as a phase accumulator. Peter Alfke, Xilinx Application

Reply to
Peter Alfke

For people that worry about the small frequency difference between the "24 Mhz/ 13" and the "PC std UART frequency" of 1.8432 MHz it might be of interest to know that the modern PC UART clock frequency is generated from 24 Mhz run through a divide by 13.

Trying to get exactly 1,8432 Mhz will thus increase your error!

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Reply to
Ulf Samuelsson

constant input of 1.8432*2^32/24. The msb of the output is your clock. Anyone please correct me if I'm wrong.

First, you're correct. 1.8432*2^32/24 into a 32-bit accumulator works fine. A straight divide-by-13 is close as well.

If you want the exact average frequency, you can also have a smaller implementation with more deterministic performance (when you have a 13-clock cycle versus when you have a 14-clock cycle) by implementing a 48/625 DDS instead of a 329853488/2^32 DDS. Rather than using a 32-bit accumulator, use a 10-bit accumulator and add 48 on most cycles but when the accumulator overflows, add 48+1024-625=447 for the single cycle instead. Coded properly, the only extra resources needed in most FPGAs is the overflow detect; the two constants are hard-coded and selected with a single bit within the accumulator logic.

Closer to 50% duty cycle with the MSbit of the accumulator can be achieved with other tricks.

Reply to
John_H

13-clock

DDS

accumulator,

accumulator

overflow

bit

achieved

When I want to generate a fixed fractional frequency like this rather than generating a general purpose DDS, I usually code it with two counters. First I figure the divide ratio as a compound fraction, in this case 13 1/48. Then the first counter is coded as divide by 13 or 14 with 1 input to select the divide ratio. The second counter divides the output of the first by 48 in this case and selects the divide-by-14 mode of the first counter every

48th cycle as it wraps. When I'm looking for a baud rate clock, I generally want a single cycle output to use as a clock enable, so the wrap of the first counter is easy to use for this. Generating a 50% (mostly) duty cycle is not too hard for the divide by 13 or 14 counter.

This whole discussion is of course off the original thread, which was about generating a stable (as in low jitter) clock using the DCM's.

Reply to
Gabor

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