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How to Find false path in a design

Hi Guys

We have been knowing the false path and its nature but i am confused as to how to identify a false path in a design having say 100 modules. We know that false path as defination that it is the path that is never executed or sanitisized henceforth it is not included in the STA . But the million dollar question is if the design is really big the how can one it so as to name it in the synthesis. I want to know the steps followed in the industry. I will value your comments and pls do upload some relevant material or any case study

Thanks in advance Vips

Reply to
VIPS
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Google for "false path" is a good start. Here's a couple of places you might look:

PrimeTime, probably the best-known of the many static timing analysis tools....

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FishTail, an interesting new tool that uses formal techniques to identify false and multi-cycle paths....

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Note, these are not recommendations in any way - just two products that I happen to be aware of. I'm sure there are many more. It's not really my field.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Reply to
Jonathan Bromley

Hi Vips,

If you are not meeting timing and you have lots and lots of path failing then save yourself some major pain and get a copy of fishtail. I played with this software some time ago and I can tell you it is very powerful. You just feed it your rtl and some constraints and out come a set of SDC files for false and multi-cycle path. On top of that if can also generate a set of assertions for you to verify the generated constraints.

Hans

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Reply to
hans64

I use separate modules for each clock domain and run STA on those. I use "known good" synchronization techniques between the modules.

-- Mike Treseler

Reply to
Mike Treseler

I should also have mentioned Blue Pearl's products...

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I talked with some of the Blue Pearl guys at DAC today and they assured me their tools can find false paths that cross design hierarchy boundaries in designs up to at least a million gates. I haven't yet had a chance to try out for myself this interesting application of formal technology.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.
Reply to
Jonathan Bromley

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