How to direct download to SRAM on Xilinx Spartan3?

Thanx!!!!!

I'm trying to understand something about UART, I've downloaded some IP cores, some app notes... But if I'll add to my design a very simple UART, with a little controller, how can i communicate with that? I downloaded the core UART from

formatting link

can I read/load data from/to it with Windows Hyperterminal (I have win2000)? And how?

Here's the miniUART entity

entity miniUART is port ( SysClk : in Std_Logic; -- System Clock Reset : in Std_Logic; -- Reset input CS_N : in Std_Logic; RD_N : in Std_Logic; WR_N : in Std_Logic; RxD : in Std_Logic; TxD : out Std_Logic; IntRx_N : out Std_Logic; -- Receive interrupt IntTx_N : out Std_Logic; -- Transmit interrupt Addr : in Std_Logic_Vector(1 downto 0); -- DataIn : in Std_Logic_Vector(7 downto 0); -- DataOut : out Std_Logic_Vector(7 downto 0)); -- end entity;

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-- Architecture for miniUART Controller Unit

------------------------------------------------------------------------------- architecture uart of miniUART is ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- signal RxData : Std_Logic_Vector(7 downto 0); -- signal TxData : Std_Logic_Vector(7 downto 0); -- signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register -- CSReg detailed -----------+--------+--------+--------+--------+--------+--------+--------+ -- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)| -- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr | -----------+--------+--------+--------+--------+--------+--------+--------+ signal EnabRx : Std_Logic; -- Enable RX unit signal EnabTx : Std_Logic; -- Enable TX unit signal DRdy : Std_Logic; -- Receive Data ready signal TRegE : Std_Logic; -- Transmit register empty signal TBufE : Std_Logic; -- Transmit buffer empty signal FErr : Std_Logic; -- Frame error signal OErr : Std_Logic; -- Output error signal Read : Std_Logic; -- Read receive buffer signal Load : Std_Logic; -- Load transmit buffer ----------------------------------------------------------------------------- -- Baud rate Generator ----------------------------------------------------------------------------- component ClkUnit is port ( SysClk : in Std_Logic; -- System Clock EnableRX : out Std_Logic; -- Control signal EnableTX : out Std_Logic; -- Control signal Reset : in Std_Logic); -- Reset input end component; ----------------------------------------------------------------------------- -- Receive Unit ----------------------------------------------------------------------------- component RxUnit is port ( Clk : in Std_Logic; -- Clock signal Reset : in Std_Logic; -- Reset input Enable : in Std_Logic; -- Enable input RxD : in Std_Logic; -- RS-232 data input RD : in Std_Logic; -- Read data signal FErr : out Std_Logic; -- Status signal OErr : out Std_Logic; -- Status signal DRdy : out Std_Logic; -- Status signal DataIn : out Std_Logic_Vector(7 downto 0)); end component; ----------------------------------------------------------------------------- -- Transmitter Unit ----------------------------------------------------------------------------- component TxUnit is port ( Clk : in Std_Logic; -- Clock signal Reset : in Std_Logic; -- Reset input Enable : in Std_Logic; -- Enable input Load : in Std_Logic; -- Load transmit data TxD : out Std_Logic; -- RS-232 data output TRegE : out Std_Logic; -- Tx register empty TBufE : out Std_Logic; -- Tx buffer empty DataO : in Std_Logic_Vector(7 downto 0)); end component; begin ----------------------------------------------------------------------------- -- Instantiation of internal components ----------------------------------------------------------------------------- ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset); TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData); RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData); ----------------------------------------------------------------------------- -- Implements the controller for Rx&Tx units ----------------------------------------------------------------------------- RSBusCtrl : process(SysClk,Reset,Read,Load) variable StatM : Std_Logic_Vector(4 downto 0); begin if Rising_Edge(SysClk) then if Reset = '0' then StatM := "00000"; IntTx_N

You have to build a FSM that reads characters from the UART and turns that into operations on your SRAM.

It would probably be easier to write in software but it shouldn't be too hard a problem to do in real hardware.

I assume it would go something like this: You have an address register and a data register. Digiits get shifted into the data register. Octal or hex, your choice. Or use A through J to simplify the hardware. A couple of special characters do reads and writes. For example: A / character copies the data from the data register into the address register does a read cycle sends back the data now in the data register A $ character stores the data register at the currently addressed location. (which was loaded by a / above.) Everything else gets ignored. Or turns on an error LED. To go faster, you can automatically bump the address after each write.