How to define the Dout width of DA FIR logic Core

Hi, I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR blocks. The wordwidth of Dout is defined as the following:

DOUT[R-1:0]: FILTER OUTPUT SAMPLE R-bit-wide output sample bus for the FIR, half-band and interpolated filters. R depends on the filter parameters (data precision, coefficient precision, number of taps and coefficient optimization selection) and is always supplied as a full-precision output port to avoid any potential for overflow.

The width of DOUT(R) is out of my control for the many different FIR coefficient sets.

In my project, I would like to have the same output wordwidth of the many DA FIR blocks. Does anyone have some good idea to reach that goal? Thanks a lot.

Reply to
fl
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Typically, because of multiply-accumulation, you end up with more internal precision than you want to output from the filter. So you just need to take these outputs and round or truncate them to the wordwidth you wish. Incidentally, I'd question the use of distributed arithmetic. It doesn't make much sense in the newer architectures. I'd use the DSP48s and the fir compiler instead of the DA fir. -Kevin

Reply to
Kevin Neilson

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