How to decide Setup/Hold time values ?

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Hi,
I am using Viretx II as my target FPGA. I use Synplify Pro 8.4 for
synthesis and Xilinx ISE 7.1 for PAR. All my input/ouput data are
registered. Do I have to specify the IO delays in the constraints
editor in Synplify Pro? Even if I have to specify the IO delays, I dont
have any idea as to what values should be given. Any thumb rules to
start with?
Similarly, there is a OFFSET IN/OUT constraint in the Xilinx
constrainst editor. Right now I have left it untouched bcoz I dont know
what values are normally given for it. In my PAR report, I am seeing
the maxilum pin delay to be some 8.6 ns. Has it got something to do
with the OFFSET IN or setup time constraint? Can anyone clear my doubts
and help in specifying the setup/hold times?

Thanks & Regards,
Srini.


Re: How to decide Setup/Hold time values ?
Hi,
I am using Viretx II as my target FPGA. I use Synplify Pro 8.4 for
synthesis and Xilinx ISE 7.1 for PAR. All my input/ouput data are
registered. Do I have to specify the IO delays in the constraints
editor in Synplify Pro? Even if I have to specify the IO delays, I dont
have any idea as to what values should be given. Any thumb rules to
start with?
Similarly, there is a OFFSET IN/OUT constraint in the Xilinx
constrainst editor. Right now I have left it untouched bcoz I dont know
what values are normally given for it. In my PAR report, I am seeing
the maxilum pin delay to be some 8.6 ns. Has it got something to do
with the OFFSET IN or setup time constraint? Can anyone clear my doubts
and help in specifying the setup/hold times?

Thanks & Regards,
Srini.


Re: How to decide Setup/Hold time values ?

Quoted text here. Click to load it

Synthesis constraints are needed to give information to the synthesis
tools to allow it to generate a reasonable implementation of your
design.  If all inputs/outputs are in registers in the IOB, there
should be no need for synthesis timing constraints on inputs/outputs.

To avoid confusion, probably best to turn off forward annotation of
timing constraints (or delete the .ncf file after synthesis).


Quoted text here. Click to load it

What does your system require?  For an input, where is the input
coming from?  Is it on the same clock, or a clock with a timing
relationship to the FPGA register clock?  If so, then do a calculation
something like the following:

Required setup time = (clock period)
                    - (external part clock to out)
                    - (trace delay 80 ps/cm)

My personal habit is to document all of the timing calculations in the
.ucf file as comments.  Open it as a text file and type in something
like this:


#
###############################################################################
#
# Data blah blah blah Output Requirement
#
#    Calculate foo to blah
# Based on rev 11.2 of Some Semiconductor Company's Part
#    Clock Period                       = 10.4 ns
#    foobar output     (Spec reference) = (1.4  ns + 0.15 ns/pf)
#    Fanout = 3, estimate cap = 15 pf   = (1.4  ns + 0.8 ns)
#                                       =  2.2 ns
#    Data (from blah) = 1/2 clk + Yahda =  5.2 ns + 2.2 ns
#                                       =  6.4 ns
#    Trace delay = 80ps/cm * 12 cm      =  0.96 ns
#
# Allowed time = Clock period - (Foobar) - (Yahda) - Trace
#              =   10.4 ns    - 2.2 ns   - 6.4 ns  - 0.96 ns
#              = 3.77 ns
# Note: This assumes jitter isn't a factor
#
INST "SOMEPINS<*>"  TNM = "DUT_OUT_GRP";
#
TIMEGRP "DUT_OUT_GRP" OFFSET = OUT    3.77 NS AFTER "NAME_OF_CLOCK";
#
#########################################################################


The example is made up, of course.  If it was real, I would have
checked and rechecked any math, checked and recheck the specification
references, and tried to make sure that it was easy to understand.

To make sure that an input with no external timing requirements is in
the IOB, I do something like this:


#########################################################################
#
# Data from FOO inputs
# These pins should be registered in the IOB FFs.  This timespec
# checks that this is correct.
# Data sheet registered time = 1.1 ns
#
INST "FOO<*>"       TNM = "FOO_IN_GRP";
#
TIMEGRP "FOO_IN_GRP" OFFSET = IN   1.2 NS BEFORE "CLOCK";
#
#########################################################################

Look in the data sheet for the registered setup or clock to output
time is.  Remember to adjust for IO standard, and for any DCM or PLL
settings.


--
Phil Hays


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