How to decide Fanout limit?

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Hi,
In Synplify Pro, there is a 'Fanout Guide' option. What is the
reasonable value for this option? How to decide the Fanout value. Is
there any thumb rule sort of thing for this?

Thanks & Regards,
Srini.


Re: How to decide Fanout limit?

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Yes, I'd guess the fanout limit to be reached when
the signal becomes marginal at the targetted inputs,
meaning the driver is at its limit.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Re: How to decide Fanout limit?
I don't know about the Synplify fanout support, but here's my $.02 on
fanout. Set it really high, like 10000. Then, after something fails
timespec, go back and manually increase registers on a per-register
basis for any register outputs that failed timespec. It is mostly an
issue with offset constraints on output data where the tristate switch
driver has to be there in < 2ns. The problem with it is that not all
tools will automatically duplicate registers to meet the fanout
constraint, and some will duplicate to meet it when it was not
necessary to meet the time constraint, thus wasting resources.


Re: How to decide Fanout limit?
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I don't think there's any one answer.  For my designs where I keep the
timing tight and the logic cones short, the fanout limit often causes more
problems than it solves.  Since the Xilinx architecture I target has drivers
at each node when the signal splits off in a chaotic tree to get to all the
destinations, there isn't a "load" that makes the signal less reliable as
the situation might be when loading many inputs off a physical wire.

If your target architecture has fanout recommendations, consider those.  If
the timing analysis from your back end tools (and from SynplifyPro) suggest
you're fine with timing, don't worry about fanout unless experience or
literature suggests there's a problem.

When I have one signal feeding every bit in multiple adders, for instance,
the signal is cleanly distributed in my FPGA yet the number of connections
would cause the fanout limit to replicate.  As with register duplication,
this second signal is too-often combined with the original signal to make a
4-input LUT break out into 2 levels of logic because there are now 5 signals
for the function, two of which are exact copies.

I'd like to see reasons anyone else might choose to apply a real fanout
limit.



Re: How to decide Fanout limit?
Hi,
My target architecture is ViretxII FPGA. I dont know whether there is
any fanout limitation or not. But I was of the opinion that a driver
having a high fanout might affect the timing in my design and I kept it
to minimum(100). I could see some synthesis notes telling that some of
the nets were replicated 'x' times bcoz of soft fanout limit of 100. I
am meeting my timing constraints with this spevs. Now, if I increase
the fanout limit to the default value of 10,000, will it affect my
timing or will there be any change in the synthesis results?


Re: How to decide Fanout limit?
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If there were notes saying the nets were replicated, there will be
changes in the synthesis results, though probably minor.

The only way to find out if timing is an issue is to rerun your
synthesis and place & route to see if your timing is worse (and by how
much) or better!

Re: How to decide Fanout limit?
srini,

Virtex II was the first family to boast of having (almost) fully
buffered Interconnect.

One of the advantages was that placement and routing could be done much
faster by our software with little thought made to inserting buffers (as
buffers were not required).

With the buffering built into each path, the use of the path provided
the proper drive, without the user having to be concerned.

Virtex II was the beginning of the cacth phrase:  "we do the ultra deep
submicron engineering, so you don't have to."

It was also the beginning of significant use of FPGAs as a solution
instead of designing their own ASIC, so we had to train many ASIC
engineers that were used to designing their own clock trees, and solving
signal buffering issues, to 'trust' us (which was completely unnatural
for them, yet there was no reason for them to worry about all these ASIC
issues, as we had already solved them).

As others have already indicated, play around, and see what makes a
difference.

Get comfortable with the technology.

But, I would encourage you to start a new design with a newer part.  Not
that Virtex II is obsolete (it and the Virtex II Pro are the most
successful and profitable FPGA lines in history), but the Virtex 4 is
much more power efficient, and less cost per function, and has superior
signal integrity with the SparseChevon(tm) package.

Austin

Re: How to decide Fanout limit?
Hi Austin,
Thanks for your detailed explanation. I will try the options and try to
get comfortable with capability of the device.

Srini.


Re: How to decide Fanout limit?
Replication can help timing mostly by generating more placement
freedom.   Actual loading effects are minimized in modern FPGAs
by buffering in the routing.   Synplify will automatically perform
some replication based on estimated timing, but tries to avoid
increasing the area to much because that can backfire.   A fanout
constraint is most useful when you discover that Synplify's timing estimates
have diverged from P&R results and use it surgically to force some
replication.   A good alternative is to use Synplify Premier which
performs full placement and local routing (on singles and doubles).
Timing in Synplify Premier correlates much better with final P&R so
it optimizes in the right places.

- Ken
CTO
Synplicity, Inc.


srini wrote:

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