How to Connect User-Defined Master Peripheral to SDRAM Slave Peripheral in SOPC Builder

I developed a custom state machine design as a Master Peripheral using the Avalon Bus specifications. The purpose of this peripheral is to read/write to external memory (i.e. SDRAM). I then include this in SOPC Builder as a User-Defined Logic and define it as a Master Peripheral and associate my top-level entity ports to the appropriate names for the Avalon Bus. When I include the SDRAM controller as a slave, the SOPC Builder indicates that the Master is not connected to the slave, and the Slave is not connected to a Master. Since this is an off-chip device, I include an Avalon Tri-state Bridge into SOPC builder in order to allow SOPC Builder to automatically connect the Master to the Slave. However, when I do so, the message window indicates the contrary. The message I receive is as follows:

tri_state_bridge_0/avalon_slave is not connected to any Master. Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is the SDRAM controller (as defined within the Memory devices in the System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral (user-defined of course) to the SDRAM controller slave? Why does the tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master + tristate bridge + SDRAM controller everything is connected with no errors. The only difference that I see is that my Master is a user-defined peripheral.

Regards, Pino

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Pino
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