Hi, I want to put a column of independent SRL16 in a Virtex 4 xc4vlx15 continuously. For even number, there is no problem. For odd number, I cannot make them continuously even though these SRL16s are parallel, independently with each other, see below code. I tried BEL attribute without success. It seems ISE9.2i has to put "G" first, again here does not require these SRL16 serially connected. Is it possible to put independent SRL16 in a straight column? Thanks in advance.
........ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.VComponents.all;
entity srl16TMP is generic ( WIDTH : in natural := 5; DELAY_DEPTH : in natural := 3); port ( S_IN : in std_logic_vector(WIDTH-1 downto 0); CLK : in std_logic; Q15 : out std_logic_vector(WIDTH-1 downto 0); S_OUT : out std_logic_vector(WIDTH-1 downto 0)); end;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.VComponents.all; architecture DELAY_COMPONENT of srl16TMP is attribute RLOC: string; attribute BEL: string; attribute INIT: string;
signal TMP0: INTEGER; CONSTANT SRL16_WIDTH : integer := 4; signal TMPVECS: STD_LOGIC_VECTOR (SRL16_WIDTH-1 downto 0); begin TMP0