Hi All:
I am trying to add my custmozied IP with DCM module in it using FSL channel. I am facing problem adding DCM module generated from IP & Architecture Wizard.
I tried this: I used the DCM vhd file created by IP & Arch wizard and added the same in .pao file. It created timing constraint problem particularly in DCM module. I face this problem because I used the wizard created DCM vhd file? How can I overcome this problem? Is there any other way that I can use DCM module in my customized IP?
Please help me out.
The DCM vhd file that I used and the timing constraint details given below (Please note that I changed the component under the label "CLKIN_BUFG_INST" to "BUFG". As per original vhd file, the component instantiated was "IBUFG". But it gave me the error ERROr:NgdBuild: 445 logical net 'xxx' has multiple drivers'. When I changed it to BUFG, I did not face the ngdbuild error: 455):
library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL;
-- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity DCM_Module is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKDV_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end DCM_Module;
architecture BEHAVIORAL of DCM_Module is signal CLKDV_BUF : std_logic; signal CLKFB_IN : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND : std_logic; component BUFG port ( I : in std_logic; O : out std_logic); end component;
component DCM generic( CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.000000; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := FALSE; CLKIN_PERIOD : real := 0.000000; CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DUTY_CYCLE_CORRECTION : boolean := TRUE; FACTORY_JF : bit_vector := x"C080"; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := FALSE; DSS_MODE : string := "NONE"; MAXPERCLKIN : time := 1000000 ps; MAXPERPSCLK : time := 100000000 ps; SIM_CLKIN_CYCLE_JITTER : time := 300 ps; SIM_CLKIN_PERIOD_JITTER : time := 1000 ps); port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; STATUS : out std_logic_vector (7 downto 0); LOCKED : out std_logic; PSDONE : out std_logic); end component;
begin GND CLKIN_IN, O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN);
DCM_INST : DCM generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.000000, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 10.000000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => TRUE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND, PSCLK=>GND, PSEN=>GND, PSINCDEC=>GND, RST=>RST_IN, CLKDV=>CLKDV_BUF, CLKFX=>open, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>open, STATUS=>open);
end BEHAVIORAL;
-------------------------------------------- Timing constraint not met problem:::
Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.
-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels
-------------------------------------------------------------------------------- NET "bufgp_2/IBUFG" PERIOD = 10 nS HIG | 10.000ns | 9.883ns |
9 H 50.000000 % | | |-------------------------------------------------------------------------------- PERIOD analysis for net "wpt_0/wpt_0/inst | 10.000ns | 8.254ns |
1 _WPT/Inst_DCM_Module/CLK0_BUF" derived fr | | |om NET "bufgp_2/IBUFG" PERIOD = 10 nS | | |
HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
- PERIOD analysis for net "wpt_0/wpt_0/inst | 20.000ns | 24.408ns |
rom NET "bufgp_2/IBUFG" PERIOD = 10 nS | | |
HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
1 constraint not met. Generating Pad Report.Thanks, Aroul