How to add clock delay in CPLD?

Hi,friends, To meet the Tsu requirement in my design, I think I should try to add some clock delay to the input register, how can I do that in CPLD? (not FPGA, without PLL,DLL)

Thanks!

Reply to
rat
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Hey

You could use a simple bianry counter....

bit 1 = IN Bit 2 = In/2 Bit 3 = In/4 and so on...

Kasper

Reply to
Repzak

It depends on your signals. Sometimes, you can use the opposite clock edge, to ensure stable sampling points. If that is too coarse, you can use delay passes, but they need real care. Nodes can be removed/optimised away by tool flows, or revisions in tool flows, and the delays are process dependant. ie use only when all else fails.

-jg

Reply to
Jim Granville

: rat wrote:

: > Hi,friends, : > To meet the Tsu requirement in my design, I think I should try to add some : > clock delay to the input register, how can I do that in CPLD? (not FPGA, : > without PLL,DLL)

: It depends on your signals. : Sometimes, you can use the opposite clock edge, to ensure stable : sampling points. : If that is too coarse, you can use delay passes, but they : need real care. Nodes can be removed/optimised away by tool flows, : or revisions in tool flows, and the delays are process dependant. : ie use only when all else fails.

Going off- and on-chip again gives also some delay that no optimizer will optimize away, at the expense of two pins...

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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Good idea :) But it seems that it is hard to do the simulation and timing analysis

Reply to
rat

: > Going off- and on-chip again gives also some delay that no optimizer will : > optimize away, at the expense of two pins...

: Good idea :) But it seems that it is hard to do the simulation and timing : analysis

Put the delay, taken from the data sheet, into the test bench...

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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Suppose I go off and back on using a single pin. How much software is "smart" enough to optimize that out?

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Reply to
Hal Murray

Have a look at the differences between fabric clocks, sometimes called asynchronous (but they are not), and global clocks. You usually get a timing shift between these. Alternatively consider negative edge clocks or if you are using Coolrunner2 the clock doubling features.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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Reply to
John Adair

Hi, you can try following method: take the clock input from clock oscillator to pin A of cpld, bring it out through pin B and now give it to global clock(global lines) pin, by this method you can have some delay (I/O buffer delay), but you need to scarifice two pins of cpld.

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  Insert two inverters in the clock path, assign output of first inv
to a io pin,(not optimized out) use the o/p of second inverter. here
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Reply to
pablo aimar

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