How powerful is Verilog at using parameters to specify designs?

Your problem now is the generate case() statements. Generate case() statements agruments DO need to be parameters. (I know I told you to change it from a localparm to a variable - but I missed the generate case() usage) However, I still don't think you should make these parameters.

Like another poster indicated - you're coding at a very low level. Instatiating "xor2" primitives and the like is quite low level. Just inline the expression using the verilog "^", "|", "&", etc operators. Change your generate case() to a procedural case().

Another comment on style. Your function should really not be both sampling, and manipulating non-local variables. Write your function with a stable API that passes in the neccesary arguments, and returns the neccesary outputs. Manipulating global variables, makes the function call pretty purposeless.

There's no reason at all for it to be a function if it's just manipulating global variables. Just move it down to the procedural block if you don't want to solidify the API. Or put it in it's own procedural block. Change the function to: always @* begin //function contents that manipulate ndTypes[]; end

Regards, Mark

Reply to
gtwrek
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Gtwrek (Mark): "Like another poster indicated - you're coding at a very low level. Instatiating 'xor2' primitives and the like is quite low level. Jus t inline the expression using the verilog '^', '|', '&', etc operators." Wh at's wrong with writing Verilog at a low level? If someone has a feel for h ow her/his design should work at a low level, is there something wrong with coding it at that level? If so, what is wrong with it?

"Change your generate case() to a procedural case()." What exactly is a pro cedural case, and how can I find out about it?

Reply to
Kevin Simonson

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